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publication number s75ws-n-00 revision a amendment 0 issue date february 17, 2005 s75ws256nxx based mcps stacked multi-chip product (mcp) 256 megabit (16m x 16-bit) cmos 1.8 volt-only simultaneous read/write, burs t-mode flash memory with 128 mb (8m x 16-bit ) cellularram and 512 mb (32m x 16-bit) data storage data sheet preliminary notice to readers: this document states the curre nt technical specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information this page intentionally left blank.
publication number s75ws-n-00 revision a amendment 0 issue date february 17, 2005 general description the s75ws-n series is a product line of stacked multi-chip product (mcp) packages and consists of the following items: ? one or more s29wsxxxn code flash ? cellularram ? one or more s29rs-n data storage flash the products covered by this document are listed in the table below: distinctive characteristics mcp features ? power supply voltage of 1.7 v to 1.95 v ? high performance ? 54 mhz, 66 mhz ? packages ?9 x 12 mm 84 ball fbga ? operating temperature ? wireless, ?25c to +85c s75ws256nxx based mcps stacked multi-chip product (mcp) 256 megabit (16m x 16-bit) cmos 1.8 volt-only simultaneous read/write, burs t-mode flash memory with 128 mb (8m x 16-bit) cellularram and 512 mb (32m x 16-bit) data storage data sheet preliminary device code flash density ram density data storage flash density 256 mb 128 mb 512 mb s75ws256ndf ?? ?
2 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notice on data sheet designations spansion llc issues data sheets with advance information or preliminary designations to advise readers of product information or intended specif ications throughout the product life cycle, includ- ing development, qualification, initial production , and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de- sign. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe- cific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the prod- uct may discontinue. spansion llc therefore pl aces the following conditions upon advance information content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the pr oduct development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initia l production, and the subsequent phases in the manufacturing process that occur before full prod uction is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as- pects of production under consideration. span sion places the following conditions upon preliminary content: ?this document states the current technical specific ations regarding the spansion product(s) described herein. the preliminary status of this document indi cates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a combination of products with different designations (advance in- formation, preliminary, or full production). this type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the dc characteristics table and the ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to th e notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designat ion is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option , temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incor- rect specification. spansion llc applies the follo wing conditions to documents in this category: ?this document states the current technical specific ations regarding the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 3 advance information contents s75ws256nxx based mcps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 input/output descriptions and logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 connection diagrams/physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 special handling instructions for fbga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 connection diagram ? cellular ram-based pinout, 9 x 12 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.1 physical dimensions ? xxx084 ? fine pi tch ball grid array 9 x 12 mm . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 look-ahead connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 s29pl256n mirrorbit? flash family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 product overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.3 synchronous (burst) read mode and configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3.1 continuous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3.2 8-, 16-, 32-word linear burst read with wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3.3 8-, 16-, 32-word linear burst without wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.4 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.5.1 single word programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.5.2 write buffer programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.5.3 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.5.4 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5.5 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5.6 program suspend/program resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.5.7 accelerated program/chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.5.8 unlock bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.5.9 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.6 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.7 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.8 handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.9 hardware reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.10 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2 persistent protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.3 dynamic protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.4 persistent protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.6 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7 hardware data protection methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7.1 wp# method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7.2 acc method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7.3 low v cc write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.7.4 write pulse glitch protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.7.5 power-up write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 10 power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.2 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.3 hardware reset# input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.1 factory secured siliconsector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.2 customer secured silicon sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.3 secured silicon sector entry and secured silicon sector exit command sequences. . . . . . . . . . . . . . . . . . . . . 63 12 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.4 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.5 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.6 v cc power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.7 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.8.1 clk characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.8.2 synchronous/burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.8.3 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.8.4 ac characteristics?asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.8.5 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.8.6 erase/program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.8.7 erase and programming performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.8.8 bga ball capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.1 common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14 commonly used terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 s29pl256n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 15 product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 16 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 17 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 18 device bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18.1 requirements for asynchronous read operation (non-burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18.2 requirements for synchronous (burst) read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 18.2.1 continuous burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.2.2 8-, 16-, and 32-word linear burst with wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.2.3 8-, 16-, and 32-word linear burst without wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 18.3 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.4 rdy: ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.5 handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 18.6 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 18.7 accelerated program/chip erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 18.8 write buffer programming operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 18.9 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.10 dynamic sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.10.1 dynamic protection bit (dyb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.11 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.12 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.13 reset#: hardware reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 18.14 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 18.15 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 18.15.1 low v cc write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 18.15.2 write pulse glitch protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 5 advance information 18.15.3 logical inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 18.15.4 power-up write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 19 sector address / memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 19.1 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 19.2 set configuration register command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 19.3 read configuration register command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 19.3.1 read mode setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 19.3.2 programmable wait state configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 19.3.3 programmable wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 19.3.4 boundary crossing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 19.3.5 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.3.6 burst length configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.3.7 burst wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.3.8 rdy configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.3.9 rdy polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 19.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 19.5 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 19.6 autoselect command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 19.7 program command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 19.8 write buffer programming command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 19.8.1 unlock bypass command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 19.9 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 19.10 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 19.10.1 accelerated sector erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 20 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 20.1 program suspend/program resume commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 20.2 volatile sector protection command se t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 21 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 22 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.1 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.2 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 22.3 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 22.4 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 22.5 dq3: sector erase timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 22.6 dq1: write to buffer abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 23 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 24 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 25 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 25.1 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 26 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 27 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 28 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 29 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 29.1 v cc power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 29.2 clk characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 29.3 synchronous/burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 29.4 asynchronous mode read @ vio = 1.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 29.5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 29.6 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 29.7 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 30 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information cellularram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 31 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 32 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 32.1 power-up initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 33 bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 33.1 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 33.2 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 33.3 burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 33.4 mixed-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 33.5 wait operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 33.6 lb#/ub# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 34 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 34.1 standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 34.2 temperature compensated refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 34.3 partial array refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 34.4 deep power-down operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 35 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 35.1 access using cre . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 35.2 bus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 35.2.1 burst length (bcr[2:0]): default = continuous burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 35.2.2 burst wrap (bcr[3]): default = no wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 35.2.3 output impedance (bcr[5:4]): defaul t = outputs use full drive strength . . . . . . . . . . . . . . . . . . . . . 166 35.2.4 wait configuration (bcr[8]): default = wait tran sitions one clock before data valid/invalid . . . . 167 35.2.5 wait polarity (bcr[10]): default = wait active high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 35.2.6 latency counter (bcr[13:11]): default = three-clock latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 35.2.7 operating mode (bcr[15]): default = asynchronous operatio n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 35.3 refresh configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 35.3.1 partial array refresh (rcr[2:0]): default = full array refr esh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 35.3.2 deep power-down (rcr[4]): default = dpd disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 35.3.3 temperature compensated refresh (rcr[6:5]): default = +85oc operation . . . . . . . . . . . . . . . . . . . 170 35.3.4 page mode operation (rcr[7]): default = disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 36 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 37 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 38 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 38.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 39 how extended timings impact cellularram? operation. . . . . . . . . . . . . . . . . . . . . . . . . . 217 39.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 39.2 asynchronous write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 39.2.1 extended write timing? asynchronous write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 39.3 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 39.4 burst-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 39.5 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 40 revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 7 advance information ta b l e s table 2.1 mcp configurations and valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7.1 s29ws256n sector & memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7.2 s29ws128n sector & memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7.3 s29ws064n sector & memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8.1 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8.2 address latency (s29ws256n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8.3 address latency (s29ws128n/s29ws064n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8.4 address/boundary crossing latency (s29ws256n @ 80/66 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 8.5 address/boundary crossing latency (s29ws256n @ 54mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8.6 address/boundary crossing latenc y (s29ws128n/s29ws064n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 8.7 burst address groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8.8 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8.9 autoselect addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8.10 autoselect entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8.11 autoselect exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8.12 single word program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8.13 write buffer program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 8.14 sector erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 8.15 chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8.16 erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 8.17 erase resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 8.18 program suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8.19 program resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8.20 unlock bypass entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 8.21 unlock bypass program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 8.22 unlock bypass reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 8.23 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 8.24 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 9.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 9.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 11.1 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 11.2 secured silicon sector entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 11.3 secured silicon sector program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 11.4 secured silicon sector exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 12.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 13.1 memory array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 13.2 sector protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 13.3 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 13.4 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 13.5 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 13.6 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 18.1 device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 18.2 address latency scheme for < 56mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 18.3 address latency scheme for < 70mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 18.4 address latency scheme for < 84mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 18.5 burst address groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 19.6 sector address / memory address map for the rs512n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 19.7 programmable wait state settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 19.8 burst length configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 19.9 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 19.10 autoselect addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 19.11 write buffer command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 22.1 maximum negative overshoot waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 24.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 27.1 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 27.2 bus operations?asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 27.3 bus operations?burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 31.1 bus configuration register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 31.2 sequence and burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 31.3 output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 31.4 variable latency configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 31.5 refresh configuration register mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 31.6 128mb address patterns for par (r cr[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 31.7 64mb address patterns for par (rcr[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 31.8 32mb address patterns for par (rcr[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 33.1 electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 33.2 temperature compensated refresh specifications and cond itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 33.3 partial array refresh specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 33.4 deep power-down specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 34.1 output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 34.2 asynchronous read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 34.3 burst read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 34.4 asynchronous write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 34.5 burst write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 34.1 initialization timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 34.2 asynchronous read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 34.3 asynchronous read timing parameters using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 34.4 asynchronous read timing parameters?page mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 34.5 burst read timing parameters?single access, variable latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 34.6 burst read timing parameters?4-word burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 34.7 burst read timing parameters?4-word burst with lb#/ub# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 34.8 burst read timing parameters?burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 34.10 burst read timing parameters?bcr[8] = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 34.11 asynchronous write timing parameters?ce#-controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 34.12 asynchronous write timing parameters?lb#/ub#-controlle d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 34.13 asynchronous write timing parameters?we#-controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 34.14 asynchronous write timing parameters using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 34.15 burst write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 34.16 burst write timing parameters?bcr[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 34.17 write timing parameters?burst write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 34.18 read timing parameters?burst write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 34.19 write timing parameters?asynchronous write followed by burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 34.20 read timing parameters?asynchronous write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 34.21 asynchronous write timing parameters?adv# low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 34.22 burst read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 34.24 burst read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 34.25 asynchronous write timing parameters?we# controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 34.27 burst read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 34.28 asynchronous write timing parameters using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 34.30 write timing parameters?adv# low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 34.31 read timing parameters?adv# low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 34.33 write timing parameters?asynchronous write followed by asynchronous read . . . . . . . . . . . . . . . . . . . . 211 table 34.34 read timing parameters?asynchronous write followed by asynchronous read . . . . . . . . . . . . . . . . . . . . . 211 table 35.1 extended cycle impact on read and write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 9 advance information figures figure 5.1 connection diagram ? cellular ram-based 84-ball fine-pi tch ball grid array ........................................... ..15 figure 5.2 look ahead pinout ? 1.8 v only x 16nor + x16psram + x16mirrorbit data..............................................16 figure 8.1 synchronous/asynchronous state diagram ................ ............................................................... ............24 figure 8.2 synchronous read ..................................................................................................... .......................27 figure 8.3 single word program.................................................................................................. .......................33 figure 8.4 write buffer programming operation ................................................................................... ................37 figure 8.5 sector erase operation ............................................................................................... .......................39 figure 8.6 write operation status flowch art ..................................................................................... ...................46 figure 9.1 advanced sector protection/unp rotection .............................................................................. ...............52 figure 9.2 ppb program/erase algorithm .......................................................................................... ...................55 figure 9.3 lock register program algorith m...................................................................................... ...................58 figure 12.1 maximum negative overshoot wave form ................................................................................. ............65 figure 12.2 maximum positive overshoot waveform ................. ................................................................ ..............65 figure 12.3 test setup .......................................................................................................... .............................66 figure 12.4 input waveforms and measuremen t levels .............................................................................. .............66 figure 12.5 v cc power-up diagram .............................................................................................................. ........67 figure 12.6 clk characterization ................................................................................................ .........................69 figure 12.7 clk synchronous burst mode read..................................................................................... .................70 figure 12.8 8-word linear burst with wrap around................................................................................ .................71 figure 12.9 8-word linear burst without wrap around ............. ................................................................ ...............71 figure 12.10 linear burst with rdy set one cycle before data .. .................................................................. ..............72 figure 12.11 asynchronous mode read............................................................................................. ......................73 figure 12.12 reset timings...................................................................................................... .............................73 figure 12.13 chip/sector erase operation timings ................................................................................ ...................75 figure 12.14 asynchronous program operation timings ............................................................................. ...............76 figure 12.15 synchronous program operation timings .............................................................................. ...............77 figure 12.16 accelerated unlock bypass prog ramming timing ....................................................................... ............77 figure 12.17 data# polling timings (during embedded algorithm) .. ................................................................ ...........78 figure 12.18 toggle bit timings (during embedded algorithm) .... ................................................................. .............78 figure 12.19 synchronous data polling timings/toggle bit timings ................................................................ ............79 figure 12.20 dq2 vs. dq6 ........................................................................................................ ............................79 figure 12.21 latency with boundary crossing when frequency > 66 mhz............................................................. .......80 figure 12.22 latency with boundary crossing into program/erase bank ............................................................. .........81 figure 12.23 example of wait state inse rtion .................................................................................... ......................82 figure 12.24 back-to-back read/write cycl e timings .............................................................................. .................83 figure 19.1 synchronous/asynchronous state diagram ................ .............................................................. ........... 110 figure 19.2 program word operation.............................................................................................. .................... 115 figure 19.3 write buffer programming operation .................................................................................. ............... 116 figure 20.4 erase operation ..................................................................................................... ......................... 119 figure 22.5 data# polling algorithm ............................................................................................. ...................... 122 figure 22.6 toggle bit algorithm ................................................................................................ ........................ 123 figure 22.7 maximum positive overshoot waveform ................. ................................................................ ............ 125 figure 24.1 test setup .......................................................................................................... ........................... 127 figure 24.2 input waveforms and measuremen t levels .............................................................................. ........... 127 figure 25.1 v cc power-up diagram .............................................................................................................. ...... 128 figure 25.2 clk characterization ................................................................................................ ....................... 128 figure 25.3 clk synchronous burst mode read..................................................................................... ............... 130 figure 25.4 8-word linear burst with wrap around................................................................................ ............... 131 figure 25.5 8-word linear burst without wrap around ............. ................................................................ ............. 131 figure 25.6 burst with rdy set one cycle before data............................................................................ .............. 132 figure 25.7 asynchronous mode read with latched addresses ....................................................................... ........ 133 figure 25.8 asynchronous mode read.............................................................................................. ................... 133 figure 25.9 reset timings....................................................................................................... .......................... 134 figure 25.10 asynchronous program operation timings: we# latched addresses ...................................................... 136
10 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information figure 25.11 synchronous program operation timings: clk latched addresses ....................................................... .. 137 figure 25.12 accelerated unlock bypass prog ramming timing ....................................................................... .......... 137 figure 25.13 data# polling timings (during embedded algorithm) .. ................................................................ ......... 138 figure 25.14 toggle bit timings (during embedded algorithm) .... ................................................................. ........... 138 figure 25.15 synchronous data polling timings/toggle bit timings ................................................................ .......... 139 figure 25.16 dq2 vs. dq6 ........................................................................................................ .......................... 139 figure 25.17 latency with boundary crossing..................................................................................... ................... 140 figure 25.18 example of wait states inse rtion ................................................................................... ................... 140 figure 25.19 back-to-back read/write cycl e timings .............................................................................. ............... 141 figure 27.1 functional block diagram ............................................................................................ ..................... 144 figure 28.2 power-up initialization timing...................................................................................... ..................... 148 figure 29.1 read operation (adv# low)........................................................................................... .................. 149 figure 29.2 write operation (a dv# low) .......................................................................................... .................. 150 figure 29.3 page mode read operation (adv # low)................................................................................. ............ 151 figure 29.4 burst mode read (4-word burst) ...................................................................................... ................. 152 figure 29.5 burst mode write (4-word burst) ..................................................................................... .................. 152 figure 29.6 wired or wait configuration........................ ................................................................. ..................... 153 figure 29.7 refresh collision during read operation............................................................................. ................ 154 figure 29.8 refresh collision during write operation ............................................................................ ................ 155 figure 31.1 configuration register write, asynchronous mode fo llowed by read .................................................... .. 158 figure 31.2 configuration register write, synchronous mode followed by read0 ........ ............................................ .. 159 figure 31.3 wait configuration (bcr[8] = 0) ........................ ............................................................. .................. 162 figure 31.4 wait configuration (bcr[8] = 1) ........................ ............................................................. .................. 162 figure 31.5 wait configuration during burs t operation ........................................................................... .............. 163 figure 31.6 latency counter (variable initia l latency, no refresh collision) .................................................... ......... 163 figure 34.1 ac input/output reference wave form .................................................................................. ............. 170 figure 34.2 output load circuit ................................................................................................. ........................ 170 figure 34.3 initialization period............................................................................................... ........................... 174 figure 34.4 asynchronous read ................................................................................................... ...................... 175 figure 34.5 asynchronous read using adv# ........................................................................................ ............... 177 figure 34.6 page mode read ...................................................................................................... ....................... 179 figure 34.7 single-access burst read operation?variable late ncy ................................................................. ........ 181 figure 34.8 four-word burst read operation?variable latency. .................................................................... ......... 183 figure 34.9 four-word burst read operation (with lb#/ub#) ....................................................................... ......... 185 figure 34.10 refresh collision during write operation ........................................................................... ................. 187 figure 34.9. continuous burst read showing an output delay with bcr[8] = 0 for end-of-row condition..................... 188 figure 34.11 ce#-controlled asynchronous write .................................................................................. ................ 189 figure 34.12 lb#/ub#-controlled asynchronous write ............... ............................................................... ............. 191 figure 34.13 we#-controlled asynchronous write.................................................................................. ................ 193 figure 34.14 asynchronous write using adv# ...................................................................................... ................. 195 figure 34.15 burst write operation ............................... ............................................................... ........................ 197 figure 34.16 continuous burst write showing an output delay wi th bcr[8] = 0 for end-of-row condition .................... 198 figure 34.17 burst write followed by burst read ................................................................................. .................. 199 figure 34.18 asynchronous write followed by burst read .......................................................................... ............. 200 figure 34.19 asynchronous write (adv# low) followed by burst re ad ............................................................... ...... 202 figure 34.23. burst read followed by asynchronous write (we#-con trolled)........................................................ ...... 204 figure 34.26. burst read followed by asynchronous write using ad v# .............................................................. ....... 206 figure 34.29. asynchronous write followed by asynchronous read?adv# low ......................................................... .208 figure 34.32. asynchronous write followed by asynchronous read .................................................................. ......... 210 figure 35.1 extended timing for t cem ............................................................................................................................ ................... 212 figure 35.2 extended timing for t tm ............................................................................................................................. .................... 212 figure 35.3 extended write operation ............................................................................................ .................... 213
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 11 advance information 1 product selector guide b note: 0 (protected), 1 (unprotected [default state]) device model numbers mcp configuration code flash density (mb) ram density (mb) data storage flash density (mb/gb) flash speed (mhz) psram speed (mhz) dyb power-up state ( see note ) psram (cellular ram) supplier package 84 ball fbga (mm) code flash code psram (mb) data storage flash s75ws256ndf ma ws256n 128 rs512n 256 128 512 mb 54 54 0 29x12 pa 1 mb 66 66 0 pb 1
12 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 2 ordering information the ordering part number is formed by a valid combination of the following: package marking note: the bga package marking omits the leading s75 and packing type designator from the ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s75ws 256 n d f ba w m a ram supplier; speed combination a = cellular ram2, 54 mhz b = cellular ram2, 66 mhz package dimensions and ball count; dyb power up; m = 1.4 mm, 9 x 12, 84 ball; 0; rs p = 1.4 mm, 9 x 12, 84 ball; 1; rs temperature range w = wireless (?25c to +85c) package type and material ba = very thin fine-pitch ball grid array (bga), lead (pb)-free compliant package bf = very thin fine-pitch ball grid array (bga), lead (pb)-free package data storage density f = 512 mb code flash density d = 128 mb process technology n = 110 nm, mirror bit technology flash density 256 = 256 mb device family s75ws = multi-chip product (mcp) 1.8-volt burst mode flash memory, ram, and nand data storage table 2.1 mcp configurations and valid combinations valid combinations s75ws256n d f ba, bf w m, p a, b
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 13 advance information 3 input/output descri ptions and logic symbol table 3.1 identifies the input and output package connections provided on the device. table 3.1 input/output descriptions symbol description a max ? a0 address inputs (common) dq15 - dq0 data inputs/outputs oe# output enable input we# write enable input v ss ground nc no connect; not connected internally. rdy ready output. indicates the status of the burst read. (flash) clk clock input. in burst mode, after the initial word is ou tput, subsequent active edges of clk increment the internal address counter. should be at v il or v ih while in asynchronous mode. (common) avd# address valid input. indicates to device that the valid addr ess is present on the address inputs. (flash) f-rst# hardware reset input. f-wp# hardware write protect input. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. f-acc accelerated input. at v hh , accelerates programming; automati cally places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. r-ce# chip-enable input for psram f-ce# chip-enable input for flash. asynchronous relative to clk for burst mode. f1-ce# chip-enable input for flash 1. f2-ce# chip-enable input for flash 2. f3-ce# chip-enable input for flash 3. r-cre control register enable . (psram ? cellularram only) f-v cc flash 1.8 volt-only single power supply. r-v cc psram power supply. r-ub# upper byte control. (psram) r-lb# lower byte control . note: r-cre is only present in cellularram-compatible psram. dq15 ? dq0 16 a max ? a0 ce# f-wp f-acc f-ce# r-ce# oe# we# f-rst# avd# r-ub# r-lb# r-cre rdy clk ( see note )
14 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 4 mcp block diagram notes: 1. cres is only present in cellularram-compatible psram. 2. ce#f1, ce#f2, and ce#f3 are the chip enable pins for the first, second, and third flash devices, respectively. ce#f3 may not be needed depending on the package. 3. if necessary. wp# acc ce# oe# we# reset# avd# dq15 ? dq0 rdy v cc flash-only address shared address clk wp# acc ce#f1 oe# we# reset# avd# v cc f ce# we# oe# ub# lb# avd# cre v cc 16 v cc s ce#s i/o15 ? i/o0 dq15 ? dq0 v ssq rdy v ss v ccq v id flash 2 flash 3 16 amax ? a0 clk ub#s lb#s cres amax ? a0 clk ce#f3 ce#f2 flash 1 psram ( note 3 ) ( note 2 )? ( note 2 )? ( note 2 )?
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 15 advance information 5 connection diagrams/physical dimensions this section contains the i/o designations and package specifications for the s75ws. 5.1 special handling instruc tions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be da maged if exposed to ultrasonic cleaning meth- ods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. 5.2 connection diagram ? cellular ram-based pino ut, 9 x 12 mm figure 5.1 connection diagram ? cellular ram-based 84-ball fine-pitch ball grid array 5.3 physical dimensions 5.3.1 physical dimensions ? xxx084 ? fi ne pitch ball grid array 9 x 12 mm tbd dnu m1 dnu m10 legend: mirrorbit? data flash only x ram only x flash shared only x x x all shared x x x dnu x x x rfu x x x x code flash only a10 dnu a1 dnu b2 adv# rfu b3 b4 clk f-vcc b6 rfu b7 rfu b8 rfu b9 b 9 rfu b5 f1-wp# c2 a7 c3 c3 c 3 c 3 r-lb# c4 we# c6 a8 c7 a11 c8 f2-ce# c9 f-acc c5 c5 c 5 c 5 a3 d2 a6 d3 r-ub# d4 rfu d6 a19 d7 d7 d 7 d 7 a12 d8 d8 d 8 d 8 a15 d9 d9 d 9 d 9 f-rst# d5 d5 d 5 d 5 a2 e2 a5 e3 a18 e4 a20 e6 a9 e7 a13 e8 a21 e9 rdy e5 a1 f2 a4 f3 a17 f4 a23 f5 f5 f 5 f 5 a10 f7 a14 f8 a22 f9 rfu f5 a0 g2 vss g3 dq1 g4 rfu g6 dq6 g7 a24 g8 a16 g9 rfu g5 f-ce# h2 oe# h3 dq9 h4 dq4 h6 dq13 h7 dq15 h8 r-cre h9 dq3 h5 r-ce1# j2 dq0 j3 dq10 j4 r-vcc j6 dq12 j7 dq7 j8 vss j9 f-vcc j5 rfu k2 dq8 k3 dq2 k4 a25 k6 dq5 k7 dq14 k8 rfu k9 dq11 k5 rfu l2 rfu l3 rfu l4 rfu l6 rfu l7 rfu l8 rfu l9 f-vcc l5
16 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 5.4 look-ahead connection diagram look ahead pinout ? 1.8 v only x 16nor + x16psram + x16mirrorbit data notes: 1. f1 and f2 denote xip/co de flash, while f3 and f4 denote data/companion flash 2. in addition to being defined as f2-ce#, ball c5 can also be assigned as f1-ce2# for code that has two chip enable signals. figure 5.2 look ahead pinout ? 1.8 v only x 16 nor + x16psram + x16mirrorbit data to provide customers with a migration path to higher densities, as well as the option to stack more die in a package, spansion has prepared a standard pinout that supports: ? nor flash and sram densities up to 4 gigabits ? nor flash and psram densities up to 4 gigabits ? nor flash and psram and data storage densities up to 4 gigabits the signal locations of the resultant mcp device are shown above. note that for different densi- ties, the actual package outline may vary. however, any pinout in any mcp will be a subset of the pinout above. legend: xram shared psram only flash/xram shared flash/data shared rfu (reserved for future use) code flash only x mirrorbit data only x x x x x x x x x x x x x x rfu b1 b10 rfu b2 rfu b9 rfu f-dqs0 n1 n1 f-dqs1 n10 rfu n2 rfu n9 rfu p1 rfu p10 p2 rfu rfu p9 a1 rfu rfu a10 rfu a2 rfu a9 d3 a7 acc d5 r-lb# d4 d7 a8 wp# d2 d8 a11 f3-ce# d9 d6 we# f3 f3 a5 f5 rdy/wait# f4 f4 a18 f7 f7 a9 f2 f2 a2 f8 f8 a13 f9 f9 a21 f6 f6 a20 j3 oe# j5 dq3 j4 dq9 j7 dq13 f1-ce# j2 j8 dq15 r-cre or r-mrs j9 j6 dq4 l3 l3 dq8 l5 l5 dq11 l4 l4 dq2 l7 l7 dq5 r-vcc l2 l8 l8 dq14 wp# l9 l6 l6 a25 c3 vss f2-ce# c5 c4 clk f-clk# c7 avd# c2 r-oe# c8 f2-oe# c9 f-vcc c6 c6 c 6 c 6 e3 a6 f-rst# c7 r-ub# d4 e7 a19 e2 a3 e8 a12 e9 a15 r1-ce2 e6 a4 g3 g3 r2-ce1 g5 a17 g4g4 a10 g7 g7 a1 g2 g2 a14 g8 g8 a22 g9 g9 a23 g6 g6 h3 h3 vss r2-vcc h5 h4 h4 dq1 h7 dq6 h2 h2 a0 h8 a24 h9 a16 r2-ce2 h6 dq0 k3 k3 f-vcc k5 dq10 k4 k4 k7 k7 dq12 r1-ce1# k2 dq7 k8 k8 k9 k9 vss r1-vcc e6 m3 a26 f-vcc m5 m4 vss r-vccq m7 m2 a27 f-vccq m8 r-clk# m9 f4-ce# m6
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 17 advance information in some cases, there may be outrigger balls in locations outside the grid shown above. in such cases, the user is recommended to treat these as rfus, and not connect them to any other signal. in case of any further inquiries about the above look-ahead pinout, please refer to the application note on this subject, or contact your spansion or fujitsu sales office.
publication number s75ws-n-00 revision a amendment 0 issue date february 17, 2005 general description the spansion s29ws256/128/064n are mirrorbit? flash products fabricated on 110 nm process technology. these burst mode flash devices are capable of perform ing simultaneous read and write operatio ns with zero latency on two separate banks using separate data and address pins. these pr oducts can operate up to 80 mhz and use a single v cc of 1.7 v to 1.95 v that makes them ideal for today?s demanding wireless applications requiring higher density, better per- formance and lowered power consumption. distinctive characteristics ? single 1.8 v read/program/erase (1.70?1.95 v) ? 110 nm mirrorbit? technology ? simultaneous read/write operation with zero latency ? 32-word write buffer ? sixteen-bank architecture consisting of 16/8/4 mwords for ws256n/128n/064n, respectively ? four 16 kword sectors at both top and bottom of memory array ? 254/126/62 64 kword sectors (ws256n/128n/ 064n) ? programmable burst read modes ? linear for 32, 16 or 8 words linear read with or without wrap-around ? continuous sequential read mode ? secured silicon sector region consisting of 128 words each for factory and customer ? 20-year data retention (typical) ? cycling endurance: 100,000 cycles per sector (typical) ? rdy output indicates data available to system ? command set compatible with jedec (42.4) standard ? hardware (wp#) protection of top and bottom sectors ? dual boot sector config uration (top and bottom) ? offered packages ? ws064n: 80-ball fbga (7 mm x 9 mm) ? ws256n/128n: 84-ball fbga (8 mm x 11.6 mm) ? low v cc write inhibit ? persistent and password methods of advanced sector protection ? write operation status bits indicate program and erase operation completion ? suspend and resume commands for program and erase operations ? unlock bypass program command to reduce programming time ? synchronous or asynchronous program operation, independent of burst control register settings ? acc input pin to reduce factory programming time ? support for common fl ash interface (cfi) ? industrial temperature range (contact factory) performance characteristics s75ws-n mirrorbit? flash family s29ws256n, s29ws128n, s29ws064n 256/128/64 megabit (16/8/4 m x 16-bit) cmos 1.8 volt-only simultaneous read/write, burst mode flash memory data sheet preliminary read access times speed option (mhz) 80 66 54 max. synch. latency, ns (t iacc ) 80 80 80 max. synch. burst access, ns (t bacc ) 9 11.2 13.5 max. asynch. access time, ns (t acc ) 80 80 80 max ce# access time, ns (t ce ) 80 80 80 max oe# access time, ns (t oe ) 13.5 13.5 13.5 current consumption (typical values) continuous burst read @ 66 mhz 35 ma simultaneous operation (asynchronous) 50 ma program (asynchronous) 19 ma erase (asynchronous) 19 ma standby mode (asynchronous) 20 a typical program & erase times single word programming 40 s effective write buffer programming (v cc ) per word 9.4 s effective write buffer programming (v acc ) per word 6 s sector erase (16 kword sector) 150 ms sector erase (64 kword sector) 600 ms
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 19 advance information 6 additional resources visit www.amd.com and www.fujitsu.com to obtain the following related documents: application notes ? using the operation status bits in amd devices ? understanding burst mode flash memory devices ? simultaneous read/write vs. erase suspend/resume ? mirrorbit? flash memory write buffer programming and page buffer read ? design-in scalable wireless solutions with spansion products ? common flash interface version 1.4 vendor specific extensions specification bulletins contact your local sales office for details. drivers and software support ? spansion low-level drivers ? enhanced flash drivers ? flash file system cad modeling support ? vhdl and verilog ? ibis ? orcad technical support contact your local sales office or contact spansion llc directly for additional technical support: email us and canada: hw.support@amd.com asia pacific: asia.support@amd.com europe, middle east, and africa japan: http://edevice.fujitsu.com/jp/support/tech/#b7 frequently asked questions (faq) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 phone us: (408) 749-5703 japan (03) 5322-3324 spansion llc locations 915 deguigne drive, p.o. box 3453 sunnyvale, ca 94088-3453, usa telephone: 408-962-2500 or 1-866-spansion spansion japan limited 4-33-4 nishi shinjuku, shinjuku-ku tokyo, 160-0023 telephone: +81-3-5302-2200 facsimile: +81-3-5302-2674 http://www.spansion.com
20 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 7 product overview the s29ws-n family consists of 256, 128 and 64mbit, 1.8 volts-only, simultaneous read/write burst mode flash device optimized for today?s wireless designs that demand a large storage array, rich functionality, and low power consumption. these devices are organized in 16, 8 or 4 mwords of 16 bits each and ar e capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. these products also offer single word programming or a 32-word buffer for programming with program/erase and suspend function ality. additional features include: ? advanced sector protection methods for protecting sectors as required ? 256 words of secured silicon area for storing customer and factory secured information. the secured silicon sector is one time programmable. 7.1 memory map the s29ws256/128/064n mbit devices consist of 16 banks organized as shown in tables table 7.1 , ta b l e 7 . 2 , and ta b l e 7 . 3 . note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not exp licitly listed (such as sa005?sa017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 7.1 s29ws256n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 2 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. sa001 004000h?007fffh sa002 008000h?00bfffh sa003 00c000h?00ffffh 15 128 sa004 to sa018 010000h?01ffffh to 0f0000h?0fffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) 2 mb 16 128 1 sa019 to sa034 100000h?10ffffh to 1f0000h?1fffffh 2 mb 16 128 2 sa035 to sa050 200000h?20ffffh to 2f0000h?2fffffh 2 mb 16 128 3 sa051 to sa066 300000h?30ffffh to 3f0000h?3fffffh 2 mb 16 128 4 sa067 to sa082 400000h?40ffffh to 4f0000h?4fffffh 2 mb 16 128 5 sa083 to sa098 500000h?50ffffh to 5f0000h?5fffffh 2 mb 16 128 6 sa099 to sa114 600000h?60ffffh to 6f0000h?6fffffh 2 mb 16 128 7 sa115 to sa130 700000h?70ffffh to 7f0000h?7fffffh 2 mb 16 128 8 sa131 to sa146 800000h?80ffffh to 8f0000h?8fffffh 2 mb 16 128 9 sa147 to sa162 900000h?90ffffh to 9f0000h?9fffffh 2 mb 16 128 10 sa163 to sa178 a00000h?a0ffffh to af0000h?afffffh 2 mb 16 128 11 sa179 to sa194 b00000h?b0ffffh to bf0000h?bfffffh 2 mb 16 128 12 sa195 to sa210 c00000h?c0ffffh to cf0000h?cfffffh 2 mb 16 128 13 sa211 to sa226 d00000h?d0ffffh to df0000h?dfffffh 2 mb 16 128 14 sa227 to sa242 e00000h?e0ffffh to ef0000h?efffffh 2 mb 15 128 15 sa243 to sa257 f00000h?f0ffffh to fe0000h?feffffh 4 32 sa258 ff0000h?ff3fffh contains four smaller sectors at top of addressable memory. sa259 ff4000h?ff7fffh sa260 ff8000h?ffbfffh sa261 ffc000h?ffffffh
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 21 advance information note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not exp licitly listed (such as sa005?sa009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 7.2 s29ws128n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 1 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. 32 sa001 004000h?007fffh 32 sa002 008000h?00bfffh 32 sa003 00c000h?00ffffh 7 128 sa004 to sa010 010000h?01ffffh to 070000h?07ffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. ( see note ) 1 mb 8 128 1 sa011 to sa018 080000h?08ffffh to 0f0000h?0fffffh 1 mb 8 128 2 sa019 to sa026 100000h?10ffffh to 170000h?17ffffh 1 mb 8 128 3 sa027 to sa034 180000h?18ffffh to 1f0000h?1fffffh 1 mb 8 128 4 sa035 to sa042 200000h?20ffffh to 270000h?27ffffh 1 mb 8 128 5 sa043 to sa050 280000h?28ffffh to 2f0000h?2fffffh 1 mb 8 128 6 sa051 to sa058 300000h?30ffffh to 370000h?37ffffh 1 mb 8 128 7 sa059 to sa066 380000h?38ffffh to 3f0000h?3fffffh 1 mb 8 128 8 sa067 to sa074 400000h?40ffffh to 470000h?47ffffh 1 mb 8 128 9 sa075 to sa082 480000h?48ffffh to 4f0000h?4fffffh 1 mb 8 128 10 sa083 to sa090 500000h?50ffffh to 570000h?57ffffh 1 mb 8 128 11 sa091 to sa098 580000h?58ffffh to 5f0000h?5fffffh 1 mb 8 128 12 sa099 to sa106 600000h?60ffffh to 670000h?67ffffh 1 mb 8 128 13 sa107 to sa114 680000h?68ffffh to 6f0000h?6fffffh 1 mb 8 128 14 sa115 to sa122 700000h?70ffffh to 770000h?77ffffh 1 mb 7 128 15 sa123 to sa129 780000h?78ffffh to 7e0000h?7effffh 4 32 sa130 7f0000h?7f3fffh contains four smaller sectors at top of addressable memory. 32 sa131 7f4000h?7f7fffh 32 sa132 7f8000h?7fbfffh 32 sa133 7fc000h?7fffffh
22 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not exp licitly listed (such as sa008?sa009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 7.3 s29ws064n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 0.5 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. sa001 004000h?007fffh sa002 008000h?00bfffh sa003 00c000h?00ffffh 3 128 sa004 010000h?01ffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) sa005 020000h?02ffffh sa006 030000h?03ffffh 0.5 mb 4 128 1 sa007?sa010 040000h?04ffffh to 070000h?07ffffh 0.5 mb 4 128 2 sa011?sa014 080000h?08ffffh to 0b0000h?0bffffh 0.5 mb 4 128 3 sa015?sa018 0c0000h?0cffffh to 0f0000h?0fffffh 0.5 mb 4 128 4 sa019?sa022 100000h?10ffffh to 130000h?13ffffh 0.5 mb 4 128 5 sa023?sa026 140000h?14ffffh to 170000h?17ffffh 0.5 mb 4 128 6 sa027?sa030 180000h?18ffffh to 1b0000h?1bffffh 0.5 mb 4 128 7 sa031?sa034 1c0000h?1cffffh to 1f0000h?1fffffh 0.5 mb 4 128 8 sa035?sa038 200000h?20ffffh to 230000h?23ffffh 0.5 mb 4 128 9 sa039?sa042 240000h?24ffffh to 270000h?27ffffh 0.5 mb 4 128 10 sa043?sa046 280000h?28ffffh to 2b0000h?2bffffh 0.5 mb 4 128 11 sa047?sa050 2c0000h?2cffffh to 2f0000h?2fffffh 0.5 mb 4 128 12 sa051?sa054 300000h?30ffffh to 330000h?33ffffh 0.5 mb 4 128 13 sa055?sa058 340000h?34ffffh to 370000h?37ffffh 0.5 mb 4 128 14 sa059?sa062 380000h?38ffffh to 3b0000h?3bffffh 0.5 mb 3 128 15 sa063 3c0000h?3cffffh sa064 3d0000h?3dffffh sa065 3e0000h?3effffh 4 32 sa066 3f0000h?3f3fffh contains four smaller sectors a t top of addressable memory. sa067 3f4000h?3f7fffh sa068 3f8000h?3fbfffh sa069 3fc000h?3fffffh
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 23 advance information 8 device operations this section describes the read, program, erase, simultaneous read/write operations, handshak- ing, and reset features of the flash devices. operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see ta b l e 1 3 . 1 and ta b l e 1 3 . 2 ). the command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the com- mand. the contents of the register serve as in put to the internal stat e machine and the state machine outputs dictate the function of the device. writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to retu rn the device to the reading array data mode. 8.1 device operation table the device must be setup appropriately for each operation. ta b l e 8 . 1 describes the required state of each control pin for any particular operation. legend: l = logic 0, h = logic 1, x = don?t care, i/o = input/output. 8.2 asynchronous read all memories require access time to output array data. in an asynchronous read operation, data is read from one memory location at a time. addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asyn- chronously with the address on its inputs. the device defaults to reading array data asynch ronously after device po wer-up or hardware re- set. asynchronous read requires that the clk signal remain at v il during the entire memory read operation. to read data from the memory array, the system must first assert a valid address on a max ?a0, while driving avd# and ce# to v il . we# must remain at v ih . the rising edge of avd# latches the address. the oe# signal must be driven to v il , once avd# has been driven to v ih . data is output on a/dq15-a/dq0 pins after the access time (t oe ) has elapsed from the falling edge of oe#. ta b l e 8 . 1 d e v i c e o p e r a t i o n s operation ce# oe# we# addresses dq15?0 reset# clk avd# asynchronous read - addresses latched l l h addr in data out h x asynchronous read - addresses steady state l l h addr in data out h x l asynchronous write l h l addr in i/o h x l synchronous write l h l addr in i/o h standby (ce#) h x x x high z h x x hardware reset x x x x high z l x x burst read operations (synchronous) load starting burst address l x h addr in x h advance burst to next address with appropriate data presented on the data bus ll h x burst data out hh terminate current burst read cycle h x h x high z h x terminate current burst read cycle via reset# x x h x high z l x x terminate current burst read cycle and start new burst read cycle lx h addr in i/o h
24 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 8.3 synchronous (burst) read mode and configuration register when a series of adjacent addresses needs to be read from the device (in order from lowest to highest address), the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. after an initial access time required for the data from the first address location, subseque nt data is output synchronized to a clock input provided by the system. the device offers both continuous and linear me thods of burst read operation, which are dis- cussed in sections 8.3.1 , 8.3.2 , and 8.3.3 . since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set to enable the burst read mode. other configuration register settings include the number of wait states to insert before the initial word (t iacc ) of each burst access, the burst mode in which to operate, and when rdy indicates data is ready to be read. prior to entering the burst mode, the system shou ld first determine the configuration register set- tings (and read the current register settings if desired via the read configuration register command sequence), and then write the configuration register command sequence. see 8.3.4 and ta b l e 1 3 . 1 for further details. figure 8.1 synchronous/asynchronous state diagram the device outputs the initial word subject to the following operational conditions: ? t iacc specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs. ? configuration register setting cr13?cr11: the total number of clock cycles (wait states) that occur before valid data appears on the device outputs. the effect is that t iacc is lengthened. the device outputs subsequent words t bacc after the active edge of each successive clock cycle, which also increments the internal address counter. the device outputs burst data at this rate sub- ject to the following operational conditions: power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (cr15 = 0) set burst mode configuration register command for asynchronous mode (cr15 = 1)
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 25 advance information ? starting address: whether the address is divisible by four (where a[1:0] is 00). a divisible- by-four address incurs the least number of additional wait states that occur after the initial word. the number of additional wait states re quired increases for burst operations in which the starting address is one, two, or three loca tions above the divisible-by-four address (i.e., where a[1:0] is 01, 10, or 11). ? boundary crossing: there is a boundary at every 128 words due to the internal architecture of the device. one additional wait state must be inserted when crossing this boundary if the memory bus is operating at a high clock freq uency. please refer to the tables below. ? clock frequency: the speed at which the device is expected to burst data. higher speeds require additional wait states after the initial word for proper operation. in all cases, with or without latency, the rdy output indicates when the next data is available to be read. ta b l e s 8.2 ? 8.6 reflect wait states required for s29w s256/128/064n device s. refer to the con- figuration register table (cr11 ? cr14) and timing diagrams for more details. table 8.2 address latency (s29ws256n) word wait states cycle 0 x ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 x ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 x ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 x ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 table 8.3 address latency (s29ws128n/s29ws064n) word wait states cycle 0 5, 6, 7 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 5, 6, 7 ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 5, 6, 7 ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 5, 6, 7 ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 table 8.4 address/boundary crossing latency (s29ws256n @ 80/66 mhz) word wait states cycle 0 7, 6 ws d0 d1 d2 d3 1 ws d4 d5 d6 d7 1 7, 6 ws d1 d2 d3 1 ws 1 ws d4 d5 d6 d7 2 7, 6 ws d2 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 3 7, 6 ws d3 1 ws 1 ws 1 ws 1 ws d4 d5 d6 d7
26 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 8.5 address/boundary crossi ng latency (s29ws256n @ 54mhz) word wait states cycle 0 5 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 5 ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 5 ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 5 ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 ta b l e 8 . 6 address/boundary crossing latency (s29ws128n/s29ws064n) word wait states cycle 0 5, 6, 7 ws d0 d1 d2 d3 1 ws d4 d5 d6 d7 1 5, 6, 7 ws d1 d2 d3 1 ws 1 ws d4 d5 d6 d7 2 5, 6, 7 ws d2 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 3 5, 6, 7 ws d3 1 ws 1 ws 1 ws 1 ws d4 d5 d6 d7
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 27 advance information figure 8.2 synchronous read 8.3.1 continuous burst read mode in the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wrap around to address 000000h when it reaches the highest addressable memory location. the burst read mode continues until the system drives ce# high, or reset= v il . continuous burst mode can also be aborted by asserting avd# low and providing a new ad- dress to the device. if the address being read crosses a 128-word line boundary (as mentioned above) and the sub- sequent word line is not being programmed or erased, additional latency cycles are required as reflected by the configuration register table ( ta b l e 8 . 8 ). if the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. upon completion of status read or program or erase operation, the host can restart a burst read operation using a new ad- dress and avd# pulse. write unlock cycles: address 555h, data aah address 2aah, data 55h write set configuration register command and settings: address 555h, data d0h address x00h, data cr load initial address address = ra read initial data rd = dq[15:0] read next data rd = dq[15:0] wait t iacc + programmable wait state setting wait x clocks: additional latency due to starting address, clock frequency, and boundary crossing end of data? yes crossing boundary? no yes completed delay x clocks unlock cycle 1 unlock cycle 2 ra = read address rd = read data command cycle cr = configuration register bits cr15-cr0 cr13-cr11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles note: setup configuration register parameters
28 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 8.3.2 8-, 16-, 32-word linear burst read with wrap around in a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con- secutive addresses that are determined by the group within which the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see ta b l e 8 . 7 ). for example, if the starting address in the 8-word mode is 3ch, the address range to be read would be 38-3fh, and the burst sequence would be 3c-3d-3e-3f-38-39-3a-3bh. thus, the device outputs all words in that burst address group until all word are read, regardless of where the start- ing address occurs in the address group, and then terminates the burst read. in a similar fashion, the 16-word and 32-word li near wrap modes begin th eir burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing. 8.3.3 8-, 16-, 32-word linear burst without wrap around if wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory addres s of the selected number of words. the burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. for example, if the starting address in the 8- word mode is 3ch, the address range to be read would be 39-40h, and the burst sequence would be 3c-3d-3e-3f-40-41-42-43h if wrap around is not enabled. the next address to be read requires a new address and avd# pulse. note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which will incur the additional boundary crossing wait state. 8.3.4 configuration register the configuration register sets various operational parameters associated with burst mode. upon power-up or hardware re set, the device defaults to the asynchronous read mode, and the config- uration register settings are in their default state. the host system should determine the proper settings for the entire configuration register, an d then execute the set configuration register command sequence, before attempting burst operations. the configuration register is not reset after deasserting ce#. the configuration register can also be read using a command sequence (see ta b l e 1 3 . 1 ). the following list describes the register settings. table 8.7 burst address groups mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h,... 16-word 16 words 0-fh, 10-1fh, 20-2fh,... 32-word 32 words 00-1fh, 20-3fh, 40-5fh,...
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 29 advance information reading the configuration table. the configuration register can be read with a four-cycle com- mand sequence. see table 13.1 for sequence details. once the data has been read from the configuration register, a software reset command is required to set the device into the correct state. 8.4 autoselect the autoselect is used for manufacturer id, device identification, and sector protection informa- tion. this mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. the autoselect codes can also be accessed in-sys- tem. when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see ta b l e 8 . 9 ). the remaining address bits are don't care. the most significant four bits of the address during the third write cycle selects the bank from which the autoselect codes are read by the host. all other banks can be accessed normally for data read without exiting the autoselect mode. ? to access the autoselect codes, the host system must issue the autoselect command. table 8.8 configuration register cr bit function settings (binary) cr15 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous read mode (default) enabled cr14 boundary crossing 54 mhz 66 mhz 80 mhz s29ws064n s29ws128n n/a n/a n/a default value is 0 s29ws256n 0 1 1 0 = no extra boundary crossing latency 1 = with extra boundary crossing latency (default) must be set to 1 greater than 54 mhz. cr13 programmable wait state s29ws064n s29ws128n 011 011 = data valid on 5th active clk edge after addresses latched 100 = data valid on 6th active clk edge after addresses latched 101 = data valid on 7th active clk edge after addresses latched (default) 110 = reserved 111 = reserved inserts wait states before initial data is available. setting greater number of wait states before initial data reduces latency after initial data. (notes 1 , 2 ) s29ws256n cr12 s29ws064n s29ws128n 100 s29ws256n cr11 s29ws064n s29ws128n 101 s29ws256n cr10 rdy polarity 0 = rdy signal active low 1 = rdy signal active high (default) cr9 reserved 1 = default cr8 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) when cr13-cr11 are set to 000, rdy is active with data regardless of cr8 setting. cr7 reserved 1 = default cr6 reserved 1 = default cr5 reserved 0 = default cr4 reserved 0 = default cr3 burst wrap around 0 = no wrap around burst 1 = wrap around burst (default) cr2 cr1 cr0 burst length 000 = continuous (default) 010 = 8-word linear burst 011 = 16-word linear burst 100 = 32-word linear burst (all other bit settings are reserved) notes: 1. refer to tables 8.2 - 8.6 for wait states requirements. 2. refer to synchronous burst read timing diagrams 3. configuration register is in the default state upon power-up or hardware reset.
30 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information ? the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. ? the autoselect command may not be written while the device is actively programming or erasing. autoselect does not support simultaneous operations or burst mode. ? the system must write the reset command to return to the read mode (or erase-suspend- read mode if the bank was previously in erase suspend). see ta b l e 1 3 . 1 for command sequence details. table 8.9 autoselect addresses description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh device id, word 2 (ba) + 0eh 2230 (ws256n) 2231 (ws128n) 2232 (ws064n) device id, word 3 (ba) + 0fh 2200 indicator bits ( see note ) (ba) + 03h dq15 - dq8 = reserved dq7 (factory lock bit): 1 = locked, 0 = not locked dq6 (customer lock bit): 1 = locked, 0 = not locked dq5 (handshake bit): 1 = reserved, 0 = standard handshake dq4, dq3 (wp# protection boot code): 00 = wp# protects both top boot and bottom boot sectors. 01, 10, 11 = reserved dq2 = reserved dq1 (dyb power up state [lock register dq4]): 1 = unlocked (user option), 0 = locked (default) dq0 (ppb eraseability [lock register dq3]): 1 = erase allowed, 0 = erase disabled sector block lock/ unlock (sa) + 02h 0001h = locked, 0000h = unlocked note: for ws128n and ws064, dq1 and dq0 are reserved.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 31 advance information notes: 1. any offset within the device works. 2. ba = bank address. the bank address is required. 3. base = base address. the following is a c source code example of using the autoselect function to read the manu- facturer id. refer to the spansion low level driver user guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software develop- ment guidelines. /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (uint16 *)bank_addr + 0x000 ); /* read manuf. id */ /* autoselect exit */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* exit autoselect (write reset command) */ software functions and sample code ta b l e 8 . 1 0 autoselect entry (lld function = lld_autoselectentrycmd) cycle operation byte address word address data unlock cycle 1 write baxaaah bax555h 0x00aah unlock cycle 2 write bax555h bax2aah 0x0055h autoselect command write baxaaah bax555h 0x0090h ta b l e 8 . 1 1 autoselect exit (lld function = lld_autoselectexitcmd) cycle operation byte address word address data unlock cycle 1 write base + xxxh base + xxxh 0x00f0h
32 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 8.5 program/erase operations these devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. however, prior to any programming and or erase op- eration, devices must be setup appropriately as outlined in the configuration register ( ta b l e 8 . 8 ). for any program and or erase operations, including writing command sequences, the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or programming data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. note the following: ? when the embedded program algorithm is comple te, the device return s to the read mode. ? the system can determine the status of the pr ogram operation by using dq7 or dq6. refer to the write operation status section for information on these status bits. ? a 0 cannot be programmed back to a 1 . attempting to do so causes the device to set dq5 = 1 (halting any further operation and requiring a reset command). a succeeding read shows that the data is still 0. only erase operations can convert a 0 to a 1 . ? any commands written to the device during the embedded program algorithm are ignored except the program suspend command. ? secured silicon sector, autoselect, and cfi fu nctions are unavailable when a program oper- ation is in progress. ? a hardware reset immediately terminates th e program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming is allowed in any sequence and across sector boundaries for single word pro- gramming operation. 8.5.1 single word programming single word programming mode is the simplest method of programmi ng. in this mode, four flash command write cycles are used to program an individual flash address. the data for this pro- gramming operation could be 8-, 16- or 32-bits wide. while this method is supported by all spansion devices, in general it is not recommended for devices that support write buffer pro- gramming. see ta b l e 1 3 . 1 for the required bus cycles and figure 8.3 for the flowchart. when the embedded program algorithm is complete , the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program oper- ation by using dq7 or dq6. refer to the write op eration status section for information on these status bits. ? during programming, any command (except the suspend program command) is ignored. ? the secured silicon sector, autoselect, and cfi functions are unavailable when a program op- eration is in progress. ? a hardware reset immediately terminates the program operation. the program command se- quence should be reinitiated once the device ha s returned to the read mode, to ensure data integrity.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 33 advance information figure 8.3 single word program write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa, pd unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) fail. issue reset command to return to read array mode. perform polling algorithm (see write operation status flowchart) yes yes no no polling status = busy? polling status = done? error condition (exceeded timing limits) pass. device is in read mode.
34 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information note: base = base address. the following is a c source code example of using the single word program function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: program command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll for program completion */ 8.5.2 write buffer programming write buffer programming allows the system to write a maximum of 32 words in one program- ming operation. this results in a faster effective word programming time than the standard word programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming occurs. at this point, the system writes the number of word locations minus 1 that are loaded into the page buffer at the sector address in which programming occurs. this tells the device how many write buffer addresses are loaded with data and therefore when to expect the program buffer to flash confirm command. the number of locations to program cannot exceed the size of the write buffer or the operation aborts. (number loaded = the number of locations to program minus 1 . for example, if the sys- tem programs 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. all subsequent address/data pairs must fall within the elected-write-buffer-page. the write-buffer-page is selected by using the addresses a max - a5. the write-buffer-page addresses must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write-buffer- pages . this also means that write buffer programming cannot be performed across multiple sec- tors. if the system attempts to load programming data outside of the selected write-buffer-page , the operation aborts.) after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. note that if a write buffer address location is loaded multiple times, the address/data pair counter is decremented for every data load operation. also, the last data loaded at a location before the program buffer to flash confirm command is programmed into th e device. it is the software's re- sponsibility to comprehend ramifications of loading a write-buffer location more than once. the software functions and sample code ta b l e 8 . 1 2 single word program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 35 advance information counter decrements for each data load operation, not for each unique write-buffer-address loca- tion. once the specified number of write buffer loca tions have been loaded, the system must then write the program buffer to flash command at the sector ad dress. any other address/data write combinations abort the write buffer programming operation. the device goes busy . the data bar polling techniques should be used while monitoring the last address location loaded into the write buffer. this eliminates the need to store an ad dress in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer embedded programming operation can be suspended using the standard sus- pend/resume commands. upon successful completion of the write buffer programming operation, the device returns to read mode. the write buffer programming sequence is aborted under any of the following conditions: ? load a value that is greater than the page buffer size during the number of locations to pro- gram step . ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different wr ite-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded ), dq6 = toggle, dq5 = 0. this indicates that the write buffer programming operation was aborted. a write-to-buffer-abort reset command sequence is requ ired when using the write buffer programming features in unlock bypass mode. note that the secured silicon sector, au- toselect, and cfi functions are unavailable when a program operation is in progress. write buffer programming is allowed in any sequence of memory (or address) locations. these flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. use of the write buffer is strongly recommended for programming when multiple words are to be programmed. write buffer programming is approxim ately eight times faster than programming one word at a time.
36 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. base = base address. 2. last = last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible. the following is a c source code example of u sing the write buffer program function. refer to the spansion low level driver user guide (available on www.amd.com and www.fujitsu.com m) for general information on spansion flash memory software develop- ment guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (uint16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (uint16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *( (uint16 *)addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)addr + 0x555 ) = 0x00f0; /* write buffer abort reset */ software functions and sample code table 8.13 write buffer program (lld functions used = lld_writetobu ffercmd, lld_programbuffertoflashcmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 write buffer load command write program address 0025h 4 write word count write program address word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words. 5 to 36 load buffer word n write program address, word n word n last write buffer to flash write sector address 0029h
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 37 advance information figure 8.4 write buffer programming operation 8.5.3 sector erase the sector erase function erases one or more sectors in the memory array. (see ta b l e 1 3 . 1 and figure 8.5 ) the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pat- tern prior to electrical erase. after a successful sector erase, all locations within the erased sector contain ffffh. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than t sea occurs. dur- ing the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than t sea . write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: address 555h, data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 yes yes yes yes yes no no no no no wc = 0? write buffer abort desired? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. write to a different sector address to cause write buffer abort pass. device is in read mode. confirm command: sa 29h wait 4 s perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command
38 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information any sector erase address and command following the exceeded time-out (t sea ) may or may not be accepted. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system can monitor dq3 to determine if the sector erase timer has timed out (see dq3: sector erase timeout state indicator ). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and ad- dresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing banks. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing bank. see write operation status for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a ha rdware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 8.5 illustrates the algorithm for the erase operation. see erase/program timing for param- eters and timing diagrams. the following is a c source code example of using the sector erase function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: sector erase command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0030; /* write sector erase command */ software functions and sample code ta b l e 8 . 1 4 sector erase (lld function = lld_sectorerasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 sector erase command write sector address sector address 0030h unlimited additional sectors may be selected for erase; command(s) must be written within t sea .
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 39 advance information notes: 1. see table 13.1 for erase command sequence. 2. see the section on dq3 for informat ion on the sector erase timeout. figure 8.5 sector erase operation no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. wait 4 s perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? ? each additional cycle must be written within t sea timeout ? timeout resets after each additional cycle is written ? the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands ? no limit on number of sectors ? commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data
40 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 8.5.4 chip erase command sequence chip erase is a six-bus cycle operation as indicated by ta b l e 1 3 . 1 . these commands invoke the embedded erase algorithm, which does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprogram s and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful chip erase, all locations of the chip contain ffffh. the system is not required to pr ovide any controls or timings during these oper- ations. ta b l e 1 3 . 1 and ta b l e 1 3 . 2 in the appendix show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and ad- dresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. see write operation status for information on these status bits. any commands written during the chip erase operat ion are ignored. however, note that a hard- ware reset immediately terminates the erase oper ation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the following is a c source code example of using the chip erase function. refer to the span- sion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash me mory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */ 8.5.5 erase suspend/er ase resume commands when the erase suspend command is written during the sector erase time-out, the device imme- diately terminates the time-out period and su spends the erase operation. the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the min- imum t sea time-out period during the sector er ase command sequence. the erase suspend command is ignored if written du ring the chip erase operation. when the erase suspend command is written after the t sea time-out period has expired and dur- ing the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation. software functions and sample code ta b l e 8 . 1 5 c h i p e r a s e (lld function = lld_chiperasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 chip erase command write base + aaah base + 555h 0010h
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 41 advance information after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the de- vice erase suspends all sectors selected for erasure.) reading at any address within erase- suspended sectors produces status information on dq7-dq0. the system can use dq7, or dq6, and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to table 8.23 for information on these status bits. after an erase-suspended program operation is co mplete, the bank returns to the erase-suspend- read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. in the erase-suspend-read mode, the system ca n also issue the autoselect command sequence. see write buffer programming and autoselect for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is requ ired when writing this command. further writes of the resume command are ignored. another er ase suspend command can be written after the chip has resumed erasing. the following is a c source code example of using the erase suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: erase suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of using the erase resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: erase resume command */ *( (uint16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ 8.5.6 program suspend/pr ogram resume commands the program suspend command allows the system to interrupt an embedded programming op- eration or a write to buffer programming operation so that data can read from any non- suspended sector. when the program suspend command is written during a programming pro- cess, the device halts the programming operation within t psl (program suspend latency) and updates the status bits. addresses are don't-cares when writing the program suspend command. software functions and sample code ta b l e 8 . 1 6 erase suspend (lld function = lld_erasesuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h ta b l e 8 . 1 7 erase resume (lld function = lld_eraseresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h
42 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a program- ming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area, then user must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in program sus- pend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device re- verts to program suspend mode, and is re ady for another valid operation. see autoselect for more information. after the program resume command is written, the device reverts to programming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the system must write the program resume command (address bits are don't care ) to exit the program suspend mode and continue the programmi ng operation. further writes of the program resume command are ignored. another program suspend command can be written after the de- vice has resumed programming. the following is a c source code example of using the program suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: program suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of using the program resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: program resume command */ *( (uint16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ 8.5.7 accelerated pr ogram/chip erase accelerated single word programming, write buffe r programming, sector erase, and chip erase operations are enabled through the acc function. th is method is faster than the standard chip program and erase command sequences. the accelerated chip program and erase functions must not be used more than 10 times per sector. in addition, accelerated chip program and erase should be performed at room tem- perature (25 c 10 c). software functions and sample code ta b l e 8 . 1 8 program suspend (lld function = lld_programsuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h ta b l e 8 . 1 9 program resume (lld function = lld_programresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 43 advance information if the system asserts v hh on this input, the device automatically enters the aforementioned un- lock bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. the system can then use the write buffer load command se- quence provided by the unlock bypass mode. note that if a write-to-buffer-abort reset is required while in unlock bypass mode, the full 3-cycle reset command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embedded pro- gram or erase operation, returns the device to normal operation. ? sectors must be unlocked prior to raising acc to v hh . ? the acc pin must not be at v hh for operations other than accelerated programming and ac- celerated chip erase, or device damage may result. ? the acc pin must not be left floating or unconne cted; inconsistent behavior of the device may result. ? acc locks all sector if set to v il . acc should be set to v ih for all other conditions. 8.5.8 unlock bypass the device features an unlock bypass mode to facilitate faster word programming. once the de- vice enters the unlock bypass mode, only two write cycles are required to program data, instead of the normal four cycles. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. see the appendix for the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode.
44 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information the following are c source code examples of u sing the unlock bypass entry, program, and exit functions. refer to the spansion low level driver user?s guide (available soon on www.amd.com and www.fujitsu.com ) for general information on spansion flash ?memory software development guidelines. /* example: unlock bypass entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)bank_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; 8.5.9 write operation status the device provides several bits to determine the status of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling. the data# polling bit, dq7, indicates to the host system whether an em- bedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command se- software functions and sample code ta b l e 8 . 2 0 unlock bypass entry (lld function = lld_unlockbypassentrycmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 entry command write base + aaah base + 555h 0020h table 8.21 unlock bypass program (lld function = lld_unlockbypassprogramcmd) cycle description operation byte address word address data 1 program setup command write base + xxxh base +xxxh 00a0h 2 program command write program address program address program data table 8.22 unlock bypass reset (lld function = lld_unlockbypassresetcmd) cycle description operation byte address word address data 1 reset cycle 1 write base + xxxh base +xxxh 0090h 2 reset cycle 2 write base + xxxh base +xxxh 0000h
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 45 advance information quence. note that the data# polling is valid only for the last word being programmed in the write- buffer-page during write buffer programming. reading data# polling status on any word other than the last word to be programmed in the writ e-buffer-page returns false status information. during the embedded program algorithm, the de vice outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is comple te, the device outputs the datum programmed to dq7. the system must provide the program addr ess to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approxi- mately t psp , then that bank returns to the read mode. during the embedded erase algori thm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling pro- duces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asyn- chronously with dq6-dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-d00 appears on successive read cycles. see the following for more information: table 8.23 , write operation status , shows the outputs for data# polling on dq7. figure 8.6 , write operation status flowchart , shows the data# polling algorithm; and figure 12.17 , data# polling timings (during embedded algorithm) , shows the data# polling timing diagram.
46 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information figure 8.6 write operation status flowchart start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no notes: 1) dq6 is toggling if read2 dq6 does not equal read3 dq6. 2) dq2 is toggling if read2 dq2 does not equal read3 dq2. 3) may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4) write buffer error if dq1 of last read =1. 5) invalid state, use reset command to exit operation. 6) valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) data polling algorithm valid for all operations except advanced sector protection. device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5)
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 47 advance information dq6: toggle bit i . toggle bit i on dq6 indicates whether an embedded program or erase algo- rithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (pri or to the program or erase operation), and dur- ing the sector erase time-out. during an embedded program or erase algorith m operation, successive read cycles to any ad- dress cause dq6 to toggle. when the oper ation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately t asp [all sectors protected toggle time], then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to dete rmine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog- gling. however, the system must also use dq2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protec ted sector, dq6 toggles for approximately t pap after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling once the embed- ded program algorithm is complete. see the following for additional information: figure 8.6 , write operation status flowchart ; figure 12.18 , toggle bit timings (dur ing embedded algorithm) , and ta b l e 8 . 2 3 and ta b l e 8 . 2 4 . toggle bit i on dq6 requires either oe# or ce# to be de-asserted and reasserted to show the change in state. dq2: toggle bit ii . the toggle bit ii on dq2, when used with dq 6, indicates whether a partic- ular sector is actively erasing (that is, the embe dded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 ca nnot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distingu ish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 8.23 to compare outputs for dq2 and dq6. see the follo wing for additional information: figure 8.6 , the dq6: tog- gle bit i section, and figures 12.17 ? 12.20 . reading toggle bits dq6/dq2. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typ- ically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erases operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bi t is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then deter- mine again whether the toggle bit is toggling, sin ce the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the rese t command to return to reading array data. the remaining scenario is that the system initially de termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through succes- sive read cycles, determining the status as describe d in the previous paragr aph. alternatively, it
48 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. refer to figure 8.6 for more details. dq5: exceeded timing limits. dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 , indicating that the program or erase cycle was not successful ly completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a 1. under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timeout state indicator. after writing a sector erase command sequence, the system may read dq3 to de termine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each addi tional sector erase command. when the time-out period is complete, dq3 switches from a 0 to a 1. if the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see sector erase command sequence for more details. after the sector erase command is written, the syst em should read the status of dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure that th e device has accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algorithm ha s begun; all further commands (ex- cept erase suspend) are ignored until the erase operation is complete. if dq3 is 0 the device accepts additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each sub-sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 8.23 shows the status of dq3 relative to the other status bits. dq1: write to buffer abort. dq1 indicates whether a write to buffer operation was aborted. under these conditions dq1 produces a 1 . the system must issue the write to buffer abort reset command sequence to return the device to reading array data. see write buffer programming operation for more details. ta b l e 8 . 2 3 write operation status notes: 1. dq5 switches to 1 when an embedded program or embedd ed erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 a valid address when reading status information. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer pr ogramming operations. note that dq7# during write buffer pro gramming indicates the data-bar for dq7 data for the last loaded write-buffer address location . program suspend mode ( note 3 ) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) reading within non-program suspended sector data data data data data data write to buffer ( note 5 ) busy state dq7# to g g l e 0 n/a n/a 0 exceeded timing limits dq7# to g g l e 1 n/a n/a 0 abort state dq7# to g g l e 0 n/a n/a 1
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 49 advance information 8.6 simultaneous read/write the simultaneous read/write feature allows the host system to read data from one bank of mem- ory while programming or erasing another bank of memory. an erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). figure 12.24 , back-to-back read/write cycle timings , shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc character- istics table for read-while-program and re ad-while-erase current specification. 8.7 writing commands/command sequences when the device is configured for asynchronous read, only asynchronous write operations are allowed, and clk is ignored. when in the synchronou s read mode configuratio n, the device is able to perform both asynchronous and synchronous write operations. clk and avd# induced address latches are supported in the synchronous programming mode. during a synchronous write oper- ation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or data. during an asynchronous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e s 7.1 ? 7.3 indicate the address space that each sector occupies. the device address space is divided into sixteen banks: banks 1 through 14 co ntain only 64 kword sectors, while banks 0 and 15 contain both 16 kword boot sectors in addition to 64 kword sectors. a bank address is the set of address bits required to uniquely select a bank. similarly, a sector address is the address bits required to uniquely select a sector. i cc2 in dc characteristics represents the active current spec- ification for the write mode. ac characteristics?synchronous and ac characteristics? asynchronous read contain timing specification tables and timing diagrams for write operations. 8.8 handshaking the handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the rdy (ready) pin, which is a dedicated output and controlled by ce#. when the device is configured to operate in sync hronous mode, and oe# is low (active), the initial word of burst data becomes available after either the falling or rising edge of the rdy pin (de- pending on the setting for bit 10 in the configuration register). it is recommended that the host system set cr13?cr11 in the configuration register to the appropriate number of wait states to ensure optimal burst mode operation (see ta b l e 8 . 8 , configuration register ). bit 8 in the configuration register allows the host to specify whether rdy is active at the same time that data is ready, or one cycle before data is ready.
50 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 8.9 hardware reset the reset# input provides a hard ware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. to ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. reset# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the flash memory upon a system reset. see figures 12.5 and 12.12 for timing diagrams. 8.10 software reset software reset is part of the command set (see ta b l e 1 3 . 1 ) that also returns the device to array read mode and must be used for the following conditions: 1. to exit autoselect mode 2. when dq5 goes high during write status oper ation that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if th e device was previously in erase suspend mode. 5. after any aborted operations note: base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; the following are additional points to consider when using the reset command: ? this command resets the banks to the read and address bits are ignored. ? reset commands are ignored once erasure ha s begun until the operation is complete. ? once programming begins, the device ignores reset commands until the operation is com- plete ? the reset command may be wri tten between the cycles in a program command sequence be- fore programming begins (prior to the third cycl e). this resets the bank to which the system was writing to the read mode. software functions and sample code ta b l e 8 . 2 4 reset (lld function = lld_resetcmd) cycle operation byte address word address data reset command write base + xxxh base + xxxh 00f0h
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 51 advance information ? if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? the reset command may be also written during an autoselect command sequence. ? if a bank has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? if dq1 goes high during a write buffer prog ramming operation, the system must write the write to buffer abort reset command sequence to reset the device to reading array data. the standard reset command does not work during this condition. ? to exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset com- mand sequence [see command table for details].
52 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 9 advanced sector protection/unprotection the advanced sector protection/unprotection feat ure disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware meth- ods, which are independent of each other. th is section describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 9.1 . figure 9.1 advanced sector protection/unprotection hardware methods software methods acc = v il ( all sectors locked) wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (ppb) 6,7,8 6. 0 = sector protected, 1 = sector unprotected. 7. protect effective only if ppb lock bit is unlocked and corresponding ppb is ?1? (unprotected). 8. volatile bits: defaults to user choice upon power-up (see ordering options). 4. 0 = sector protected, 1 = sector unprotected. 5. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset. 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock. 3. n = highest address sector.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 53 advance information 9.1 lock register as shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the dyb ordering option. the device programmer or host system must then choose which sector protection method to use. program- ming (setting to 0 ) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: ? lock register persistent protection mode lock bit (dq1) ? lock register password protection mode lock bit (dq2) for programming lock register bits refer to ta b l e 1 3 . 2 . notes 1. if the password mode is chosen, the password must be programmed before setting the cor- responding lock register bit. 2. after the lock register bits command set en try command sequence is written, reads and writes for bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 3. if both lock bits are selected to be progra mmed (to zeros) at the same time, the operation aborts. 4. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled, and no changes to the protection schem e are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. after selecting a sector protection method, each sector can operate in any of the following three states: 1. constantly locked. the selected sectors are protected and can not be reprogrammed unless ppb lock bit is cleared via a password, hardware reset, or power cycle. 2. dynamically locked. the selected sectors are protected and can be altered via software commands. 3. unlocked. the sectors are unprotected and can be erased and/or programmed. these states are controlled by the bit types described in sections 9.2 ? 9.6 . 9.2 persistent protection bits the persistent protection bits are unique and nonvolatile for each sector and have the same en- durances as the flash memory. pr eprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. table 9.1 lock register device dq15-05 dq4 dq3 dq2 dq1 dq0 s29ws256n 1 1 1 password protection mode lock bit persistent protection mode lock bit customer secured silicon sector protection bit s29ws128n/ s29ws064n undefined dyb lock boot bit 0 = sectors power up protected 1 = sectors power up unprotected ppb one-time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit
54 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes 1. each ppb is individually programmed and all are erased in parallel. 2. while programming ppb for a sector, array data can be read from any other bank, except bank 0 (used for data# polling) and the bank in which sector ppb is being programmed. 3. entry command disables reads and writes for the bank selected. 4. reads within that bank return the ppb status for that sector. 5. reads from other banks are allowed while writes are not allowed. 6. all reads must be performed using the asynchronous mode. 7. the specific sector address (a23-a14 ws256n, a22-a14 ws128n, a21-a14 ws064n) are written at the same time as the program command. 8. if the ppb lock bit is set, the ppb progra m or erase command does not execute and times- out without programming or erasing the ppb. 9. there are no means for individually erasing a sp ecific ppb and no specif ic sector address is required for this operation. 10. exit command must be issued after the execut ion which resets the device to read mode and re-enables reads and writes for bank 0 11. the programming state of the ppb for a given sector can be verified by writing a ppb status read command to the device as describ ed by the flow chart shown in figure 9.2.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 55 advance information figure 9.2 ppb program/erase algorithm 9.3 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dybs only control the protection scheme for unprotected sectors that have their ppbs cleared (erased to 1 ). by issuing the dyb set or clear command sequences, the dybs are set (pro- grammed to 0 ) or cleared (erased to 1 ), thus placing each sector in the protected or unprotected state respectively. this feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. read byte twice addr = sa0 enter ppb command set. addr = ba program ppb bit. addr = sa dq5 = 1? yes yes yes no no no yes dq6 = toggle? dq6 = toggle? read byte. addr = sa pass fail issue reset command exit ppb command set dq0 = '1' (erase) '0' (pgm.)? read byte twice addr = sa0 no wait 500 s
56 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes 1. the dybs can be set (programmed to 0 ) or cleared (erased to 1 ) as often as needed. when the parts are first shipped, the ppbs are cleared (erased to 1 ) and upon power up or reset, the dybs can be set or cleared depend ing upon the ordering option chosen. 2. if the option to clear the dybs after power up is chosen, (erased to 1 ), then the sectorsmay be modified depending upon the ppb state of that sector (see table 9.2 ). 3. the sectors would be in the protected state if the option to set the dybs after power up is chosen (programmed to 0 ). 4. it is possible to have sectors that are persiste ntly locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. however, if there is a need to change the status of the per- sistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired setting s. setting the ppb lock bit once again locks the ppbs, and the device op erates normally again. 6. to achieve the best protection, it is recommended to execute the ppb lock bit set command early in the boot code and protect the boot code by holding wp# = v il . note that the ppb and dyb bits have the same function when acc = v hh as they do when acc =v ih . 9.4 persistent protection bit lock bit the persistent protection bit lock bit is a global volatile bit for all sectors. when set (programmed to 0 ), it locks all ppbs and when cleared (programmed to 1 ), allows the ppbs to be changed. there is only one ppb lock bit per device. notes 1. no software command sequence unlocks this bit unless the device is in the password pro- tection mode; only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be set (programmed to 0 ) only after all ppbs are configured to the desired settings. 9.5 password protection method the password protection method allows an even higher level of security than the persistent sector protection mode by requiring a 64 bit password for unlocking the device ppb lock bit. in addition to this password requirement, after powe r up and reset, the ppb lock bit is set 0 to maintain the password mode of operation. successful executio n of the password unlock command by entering the entire password clears the ppb lock bit, allowing for sector ppbs modifications.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 57 advance information notes 1. there is no special addressing order required for programming the password. once the password is written and verified, the password mo de locking bit must be set in order to pre- vent access. 2. the password program command is only capable of programming 0 s. programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0 . 3. the password is all 1 s when shipped from the factory. 4. all 64-bit password combinations are valid as a password. 5. there is no means to verify what the password is after it is set. 6. the password mode lock bit, once set, prev ents reading the 64-bit password on the data bus and further password programming. 7. the password mode lock bit is not erasable. 8. the lower two address bits (a1?a0) are valid during the password read, password program, and password unlock. 9. the exact password must be entered in or der for the unlocking function to occur. 10. the password unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11. approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12. password verification is only allowed during the password programming operation. 13. all further commands to the password region are disabled and all operations are ignored. 14. if the password is lost after setting the passwor d mode lock bit, there is no way to clear the ppb lock bit. 15. entry command sequence must be issued prior to any of any operation and it disables reads and writes for bank 0. reads and writes for other banks excluding bank 0 are allowed. 16. if the user attempts to program or erase a protected sector, the device ignores the com- mand and returns to read mode. 17. a program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read comm ands dyb status, ppb status, and ppb lock status to the device.
58 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information figure 9.3 lock register program algorithm write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock register can only be progammed once. wait 4 s pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 59 advance information 9.6 advanced sector protection software examples table 9.2 contains all possible combinations of the dyb, ppb, and ppb lock bit relating to the sta- tus of the sector. in summary, if the ppb lock bit is locked (set to 0 ), no changes to the ppbs are allowed. the ppb lock bit can only be unlocked (reset to 1 ) through a hardware reset or power cycle. see also figure 9.1 for an overview of the advanc ed sector protection feature. 9.7 hardware data protection methods the device offers two main types of data protec tion at the sector level via hardware control: ? when wp# is at v il , the four outermost sectors are locked (device specific). ? when acc is at v il , all sectors are locked. there are additional methods by which intended or accidental erasure of any sectors can be pre- vented via hardware means. the following subsections describes these methods: 9.7.1 wp# method the write protect feature provides a hardware meth od of protecting the four outermost sectors. this function is provided by the wp# pin and ov errides the previously discussed sector protec- tion/unprotection method. if the system asserts v il on the wp# pin, the device disables program and erase functions in the outermost boot sectors. the outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. if the system asserts v ih on the wp# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp# pin must not be left floating or unconnected as inconsistent behavior of the device may result. the wp# pin must be held stable during a command sequence execution 9.7.2 acc method this method is similar to above, except it prot ects all sectors. once acc input is set to v il , all program and erase functions are disabled and hence all sectors are protected. 9.7.3 low v cc write inhibit when v cc is less than v lko , the device does not accept any writ e cycles. this prot ects data during v cc power-up and power-down. ta b l e 9 . 2 unique device ppb lock bit 0 = locked 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status any sector 0 0 x protected through ppb any sector 0 0 x protected through ppb any sector 0 1 1 unprotected any sector 0 1 0 protected through dyb any sector 1 0 x protected through ppb any sector 1 0 x protected through ppb any sector 1 1 0 protected through dyb any sector 1 1 1 unprotected
60 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subseque nt writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . 9.7.4 write pulse glitch protection noise pulses of less than 3 ns (typical) on oe#, ce# or we# do not initiate a write cycle. 9.7.5 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept com- mands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 61 advance information 10 power conservation modes 10.1 standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is grea tly reduced, and the outputs are placed in the high impedance state, independent of the oe# in put. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in dc characteristics represents the standby current specification 10.2 automatic sleep mode the automatic sleep mode minimizes flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. stan- dard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. while in synchronous mode, the auto- matic sleep mode is disabled. note that a new bu rst operation is required to provide new data. i cc6 in dc characteristics represents the automatic sleep mode current specification. 10.3 hardware reset# input operation the reset# input provides a hard ware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current is greater. reset# may be tied to the system reset circuitr y and thus, a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. 10.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state.
62 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 11 secured silicon sector flash memory region the secured silicon sector provides an extra flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 words in length that consists of 128 words for factory data and 128 words for customer-secured areas. all secured silicon reads outside of the 256-word address range returns invalid data. the factory indicator bit, dq7, (at autoselect address 03h) is used to indicate whether or not the factory se- cured silicon sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secured silicon sector is locked when shipped from the factory. please note the following general conditions: ? while secured silicon sector access is enabled, simultaneous operations are allowed except for bank 0. ? on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. ? reads can be performed in the asynchronous or synchronous mode. ? burst mode reads within secured silicon sector wrap from address ffh back to address 00h. ? reads outside of sector 0 return memory array data. ? continuous burst read past the maximum address is undefined. ? sector 0 is remapped from memory array to secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit command must be issued to exit secured silicon sector mode. ? the secured silicon sector is not accessible wh en the device is executing an embedded pro- gram or embedded erase algorithm. 11.1 factory secured siliconsector the factory secured silicon sector is always protected when shipped from the factory and has the factory indicator bit (dq7) permanently set to a 1 . this prevents cloning of a factory locked part and ensures the security of the esn and customer code once the product is shipped to the field. these devices are available pre programmed with one of the following: ? a random, 8 word secure esn only within the factory secured silicon sector ? customer code within the customer secu red silicon sector through the spansion tm program- ming service. ? both a random, secure esn and customer code through the spansion programming service. customers may opt to have their code progra mmed through the spansion programming services. spansion programs the customer's code, with or without the random esn. the devices are then shipped from the spansion factory with the factory secured silicon sector and customer secured silicon sector permanently locked. contact your local representative for details on using spansion programming services. table 11.1 addresses sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 63 advance information 11.2 customer secured silicon sector the customer secured silicon sector is typically shipped unprotected (dq6 set to 0 ), allowing customers to utilize that sector in any manner they choose. if the security feature is not required, the customer secured silicon sector can be treated as an additional flash memory space. please note the following: ? once the customer secured silicon sector area is protected, the customer indicator bit is permanently set to 1. ? the customer secured silicon sector can be read any number of times, but can be pro- grammed and locked only once. the customer secu red silicon sector lock must be used with caution as once locked, there is no procedure available for unlocking the customer secured silicon sector area and none of the bits in th e customer secured silicon sector memory space can be modified in any way. ? the accelerated programming (acc) and unlock bypass functions are not available when pro- gramming the customer secured silicon sector, but reading in banks 1 through 15 is avail- able. ? once the customer secured silicon sector is lo cked and verified, the system must write the exit secured silicon sector region command se quence which return the device to the mem- ory array at sector 0. 11.3 secured silicon sector entry and secured si licon sector exit command sequences the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector re- gion until the system issues the four-cycle exit secured silicon sector command sequence. see command definition table [secured s ilicon sector command table, appendix table 13.1 for address and data requirements for both command sequences. the secured silicon sector entry command allows the following commands to be executed ? read customer and factory secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by sector sa0 within the memory array. this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is removed from the device.
64 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information the following are c functions and source code examples of using the secured silicon sector entry, program, and exit commands. refer to the spansion low level driver user?s guide (available soon on www.amd.com and www.fujits u.com) for general information on spansion flash memory software development guidelines. note: base = base address. /* example: secsi sector entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0088; /* write secsi sector entry cmd */ note: base = base address. /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ note: base = base address. /* example: secsi sector exit command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write secsi sector exit cycle 3 */ *( (uint16 *)base_addr + 0x000 ) = 0x0000; /* write secsi sector exit cycle 4 */ software functions and sample code ta b l e 1 1 . 2 secured silicon sector entry (lld function = lld_secsisectorentrycmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h entry cycle write base + aaah base + 555h 0088h table 11.3 secured silicon sector program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word table 11.4 secured silicon sector exit (lld function = lld_secsisectorexitcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h exit cycle write base + aaah base + 555h 0090h
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 65 advance information 12 electrical specifications 12.1 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to + 125c voltage with respect to ground: all inputs and i/os except as noted below ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v io + 0.5 v v cc ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +2.5 v acc ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +9.5 v output short circuit current ( note 3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 12.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 12.2 . 2. minimum dc input voltage on pin acc is -0.5v. during voltage transitions, acc may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 12.1 . maximum dc voltage on pin acc is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum ra ting conditions for extended periods may affe ct device reliability. note: the content in this document is advance information for th e s29ws064n and s29ws128n. co ntent in this document is preliminary for the s29w256n. 12.2 operating ranges wireless (w) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?25c to +85c industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.70 v to +1.95 v v io supply voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 v to +1.95 v (contact local sales office for v io = 1.35 to +1.70 v.) note: operating ranges define those limits between which the device functionality is guaranteed. figure 12.1 maximum negative overshoot waveform figure 12.2 maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v
66 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 12.3 test conditions figure 12.3 te s t s e t u p note: the content in this document is advance information for the s29ws064n and s2 9ws128n. content in this document is preliminary for the s29w256n. 12.4 key to switching waveforms note: the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. 12.5 switching waveforms figure 12.4 input waveforms and measurement levels table 12.1 test specifications test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 3.0 @ 54, 66 mhz 2.5 @ 80 mhz ns input pulse levels 0.0?v io v input timing measurem ent reference levels v io /2 v output timing measurement reference levels v io /2 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) c l device under test v io 0.0 v output measurement level input v io /2 v io /2 all inputs and outputs
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 67 advance information 12.6 v cc power-up notes: 1. v cc >= v io - 100mv and v cc ramp rate is > 1v / 100s 2. v cc ramp rate <1v / 100s, a hardware reset is required. 3. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. figure 12.5 v cc power-up diagram parameter description test setup speed unit t vcs v cc setup time min 1 ms v cc v io reset# t vcs
68 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 12.7 dc characteristics (cmos compatible) notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. v cc = v io . 3. ce# must be set high when measuring the rdy pin. 4. the i cc current listed is typically less than 3 ma/mhz, with oe# at v ih . 5. i cc active while embedded erase or embedded program is in progress. 6. device enters automatic sleep mode when addresses are stable for t acc + 20 ns. typical sleep mode current is equal to i cc3 . 7. v ih = v cc 0.2 v and v il > ?0.1 v. 8. total current during accelerate d programming is the sum of v acc and v cc currents. 9. v acc = v hh on acc input. 10. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter description (notes) test conditions (notes 1, 2, 9) min ty p max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current ( 3 ) v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih , burst length = 8 54 mhz 27 54 ma 66 mhz 28 60 ma 80 mhz 30 66 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 16 54 mhz 28 48 ma 66 mhz 30 54 ma 80 mhz 32 60 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 32 54 mhz 29 42 ma 66 mhz 32 48 ma 80 mhz 34 54 ma ce# = v il , oe# = v ih , we# = v ih , burst length = continuous 54 mhz 32 36 ma 66 mhz 35 42 ma 80 mhz 38 48 ma i io1 v io non-active output oe# = v ih 20 30 a i cc1 v cc active asynchronous
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 69 advance information 12.8 ac characteristics 12.8.1 clk characterization note: the content in this document is advance information for the s29ws064n and s2 9ws128n. content in this document is preliminary for the s29w256n. figure 12.6 clk characterization 12.8.2 synchronous/burst read notes: 1. addresses are latched on the first rising edge of clk. 2. not 100% tested. 3. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter description 54 mhz 66 mhz 80 mhz unit f clk clk frequency max 54 66 80 mhz t clk clk period min 18.5 15.1 12.5 ns t ch clk high time min 7.4 6.1 5.0 ns t cl clk low time t cr clk rise time max 3 3 2.5 ns t cf clk fall time parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t iacc latency max 80 ns t bacc burst access time valid clock to output delay max 13.5 11.2 9 ns t acs address setup time to clk ( note 1 )min5 4 ns t ach address hold time from clk ( note 1 )min7 6 ns t bdh data hold time from next clock cycle min 4 3 ns t cr chip enable to rdy valid max 13.5 11.2 9 ns t oe output enable to output valid max 13.5 11.2 ns t cez chip enable to high z ( note 2 )max10 ns t oez output enable to high z ( note 2 )max 10 ns t ces ce# setup time to clk min 4 ns t rdys rdy setup time to clk min 5 4 3.5 ns t racc ready access time from clk max 13.5 11.2 9 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk min 4 ns t avd avd# pulse min 8 ns t aoe avd low to oe# low max 38.4 ns t clk t cl t ch t cr t cf clk
70 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 12.8.3 timing diagrams notes: 1. figure shows total number of wait states set to five cycles . the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at address + 1 , address + 2 , or address + 3 , additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode. figure 12.7 clk synchronous burst mode read da da + 1 da + n oe# data (n) addresses aa avd# rdy (n) clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t aoe t bdh 5 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z hi-z hi-z 12 3456 7 t rdys t bacc da + 3 da + 2 da da + 1 da + n data (n + 1) rdy (n + 1) hi-z hi-z hi-z da + 2 da + 2 da da + 1 da + n data (n + 2) rdy (n + 2) hi-z hi-z hi-z da + 1 da + 1 da da da + n data (n + 3) rdy (n + 3) hi-z hi-z hi-z da da t cr
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 71 advance information notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at address + 1 , address + 2 , or address + 3 , additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode with wrap around. 4. d8?df in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 4th address in range (0-f). figure 12.8 8-word linear burst with wrap around notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at address + 1 , address + 2 , or address + 3 , additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in asynchronous mode with out wrap around. 4. dc?d13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 1st address in range (c-13). figure 12.9 8-word linear burst without wrap around dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t aoe t bdh de df db 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d8 t racc dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df d13 hi-z t racc 1234567 t rdys t bacc t cr d10 t racc t aoe 7 cycles for initial access shown.
72 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. figure assumes 6 wait states for initial access and synchronous read. 2. the set configuration register command sequence has been written with cr8=0; device outputs rdy one cycle before valid data. figure 12.10 linear burst with rdy set one cycle before data 12.8.4 ac characterist ics?asynchronous read notes: 1. not 100% tested. 2. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t ce access time from ce# low max 80 ns t acc asynchronous access time max 80 ns t avdp avd# low time min 8 ns t aavds address setup time to rising edge of avd# min 4 ns t aavdh address hold time from rising edge of avd# min 7 6 ns t oe output enable to output valid max 13.5 ns t oeh output enable hold time read min 0 ns data# polling min 10 ns t oez output enable to high z (see note) max 10 ns t cas ce# setup time to avd# min 0 ns da+1 da da+2 da+3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t aoe t bdh 6 wait cycles for initial access shown. hi-z hi-z hi-z 123456 t rdys t bacc t cr
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 73 advance information note: ra = read address, rd = read data. figure 12.11 asynchronous mode read 12.8.5 hardware reset (reset#) notes: 1. not 100% tested. 2. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. figure 12.12 reset timings parameter description all speed options unit jedec std. t rp reset# pulse width min 30 s t rh reset high time before read ( see note )min200ns t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas reset# t rp ce#, oe# t rh
74 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 12.8.6 erase/program timing notes: 1. not 100% tested. 2. asynchronous read mode allows asynchronous program operation only. synchronous read mode allows both asynchronous and synchronous program operation. 3. in asynchronous program operation timing, addresses are latched on the falling edge of we#. in synchronous program operation timing, addresses are latched on the rising edge of clk. 4. see the erase and programming performance section for more information. 5. does not include the preprogramming time. 6. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t avav t wc write cycle time ( note 1 )min80ns t avwl t as address setup time (notes 2 , 3 ) synchronous min 5ns asynchronous 0 ns t wlax t ah address hold time (notes 2 , 3 ) synchronous min 9 ns asynchronous 20 t avdp avd# low time min 8 ns t dvwh t ds data setup time min 45 20 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 ns t whwl t wph write pulse width high min 20 ns t sr/w latency between read and write operations min 0 ns t vid v acc rise and fall time min 500 ns t vids v acc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t elwl t cs ce# setup time to we# min 5 ns t avsw avd# setup time to we# min 5 ns t avhw avd# hold time to we# min 5 ns t avsc avd# setup time to clk min 5 ns t avhc avd# hold time to clk min 5 ns t csw clock setup time to we# min 5 ns t wep noise pulse margin on we# max 3 ns t sea sector erase accept time-out max 50 s t esl erase suspend latency max 20 s t psl program suspend latency max 20 s t asp toggle time during sector protection typ 100 s t psp toggle time during programming within a protected sector typ 1 s
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 75 advance information figure 12.13 chip/sector erase operation timings oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h
76 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. a23?a14 for the ws256n (a22?a14 for the ws128n, a21?a 14 for the ws064n) are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is independent of th e set device read mode bit in the configuration register. figure 12.14 asynchronous program operation timings oe# ce# data addresses avd we# clk v cc 555h pd t as t avsw t avhw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs t cas
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 77 advance information notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. a23?a14 for the ws256n (a22?a14 for the ws128n, a21?a 14 for the ws064n) are don?t care during command sequence unlock cycles. 4. addresses are latched on the first rising edge of clk. 5. either ce# or avd# is required to go from low to high in be tween programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 12.15 synchronous program operation timings note: use setup and hold times from conventional program operation. figure 12.16 accelerated unlock bypass programming timing oe# ce# data addresses we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw t avsc avd# ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id v il or v ih t vid t vids
78 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is completedata# polling outputs true data. figure 12.17 data# polling timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete, . figure 12.18 toggle bit timings (during embedded algorithm) we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 79 advance information notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete, . 3. rdy is active with data (d8 = 1 in the configuration register). when d8 = 0 in the configuration register, rdy is active one clock cycle before data. figure 12.19 synchronous data polling ti mings/toggle bit timings note: dq2 toggles only when read at an address within an er ase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6 figure 12.20 dq2 vs. dq6 ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
80 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. rdy(1) active with data (d8 = 1 in the configuration register). 2. rdy(2) active one clock cycle before data (d8 = 0 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device not crossing a bank in the process of performing an erase or program. 5. rdy does not go low and no additional wait states are re quired if the burst frequency is <=66 mhz and the boundary crossing bit (d14) in the configuration register is set to 0 figure 12.21 latency with boundary crossing when frequency > 66 mhz clk address (hex) c124 c125 c126 c127 c127 c128 c129 c130 c131 d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy(2) latency t racc t racc t racc t racc
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 81 advance information notes: 1. rdy(1) active with data (d8 = 1 in the configuration register). 2. rdy(2) active one clock cycle before data (d8 = 0 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device crossing a bank in the process of performing an erase or program. 5. rdy does not go low and no additional wait states are required if the burst frequency is < 66 mhz and the boundary crossing bit (d14) in the configuration register is set to 0 . figure 12.22 latency with boundary crossing into program/erase bank clk address (hex) c124 c125 c126 c127 c127 d124 d125 d126 d127 read status (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f latency rdy(2) latency t racc t racc t racc t racc
82 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information wait state configuration register setup: d13, d12, d11 = 111 ? reserved d13, d12, d11 = 110 ? reserved d13, d12, d11 = 101 ? 5 programmed, 7 total d13, d12, d11 = 100 ? 4 programmed, 6 total d13, d12, d11 = 011 ? 3 programmed, 5 total d13, d12, d11 = 010 ? 2 programmed, 4 total d13, d12, d11 = 001 ? 1 programmed, 3 total d13, d12, d11 = 000 ? 0 programmed, 2 total note: 6.figure assumes address d0 is not at an address boundary, and wait state is set to 101 figure 12.23 example of wait state insertion data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 83 advance information note: breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while check - ing the status of the program or erase operation in the busy bank. the system should read status twice to ensure valid information. figure 12.24 back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
84 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 12.8.7 erase and programming performance notes: 1. typical program and erase times a ssume the following conditions: 25 c, 1.8 v v cc , 10,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 1.70 v, 100,000 cycles. 3. typical chip programming time is cons iderably less than the maximum chip pr ogramming time listed, and is based on utilizing the write buffer. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see the appendix for further information about command definitions. 6. contact the local sales office for mini mum cycling endurance values in specific applications and op erating conditions. 7. refer to application note erase suspend/resume timing for more details. 8. word programming specification is based upon a single word programming operation not utilizing th e write buffer. 9. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter ty p ( note 1 )max ( note 2 ) unit comments sector erase time 64 kword v cc 0.6 3.5 s excludes 00h programming prior to erasure ( note 4 ) 16 kword v cc <0.15 2 chip erase time v cc 153.6 (ws256n) 77.4 (ws128n) 39.3 (ws064n) 308 (ws256n) 154 (ws128n) 78 (ws064n) s acc 130.6 (ws256n) 65.8 (ws128n) 33.4 (ws064n) 262 (ws256n) 132 (ws128n) 66 (ws064n) single word programming time ( note 8 ) v cc 40 400 s acc 24 240 effective word programming time utilizing program write buffer v cc 9.4 94 s acc 6 60 total 32-word buffer programming time v cc 300 3000 s acc 192 1920 chip programming time ( note 3 ) v cc 157.3 (ws256n) 78.6 (ws128n) 39.3 (ws064n) 314.6 (ws256n) 157.3 (ws128n) 78.6 (ws064n) s excludes system level overhead
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 85 advance information 12.8.8 bga ball capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c; f = 1.0 mhz. 3. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter symbol parameter description te s t s e t u p ty p . max unit c in input capacitance v in = 0 5.3 6.3 pf c out output capacitance v out = 0 5.8 6.8 pf c in2 control pin capacitance v in = 0 6.3 7.3 pf
86 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 13 appendix this section contains information relating to software control or interfacing with the flash device. for additional information and assi stance regarding software, see the additional resources on page 19, or explore the web at www.amd.com and www.fujitsu.com .
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 87 advance information table 13.1 memory array commands command sequence (notes) cycles bus cycles (notes 1?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read ( 6 )1 ra rd reset ( 7 ) 1 xxx f0 auto- select ( 8 ) manufacturer id 4 555 aa 2aa 55 [ba]555 90 [ba]x00 0001 device id ( 9 ) 6 555 aa 2aa 55 [ba]555 90 [ba]x01 227e ba+x0e data ba+x0f 2200 indicator bits ( 10 ) 4 555 aa 2aa 55 [ba]555 90 [ba]x03 data program 4 555 aa 2aa 55 555 a0 pa pd write to buffer ( 11 ) 6 555 aa 2aa 55 pa 25 pa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset ( 12 ) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase/program suspend ( 13 ) 1 ba b0 erase/program resume ( 14 ) 1 ba 30 set configuration register ( 18 ) 4 555 aa 2aa 55 555 d0 x00 cr read configuration register 4 555 aa 2aa 55 555 c6 x00 cr cfi query ( 15 ) 1 [ba]555 98 unlock bypass mode entry 3 555 aa 2aa 55 555 20 program ( 16 ) 2 xxx a0 pa pd cfi ( 16 ) 1 xxx 98 reset 2 xxx 90 xxx 00 secured silicon sector entry 3 555 aa 2aa 55 555 88 program ( 17 ) 4 555 aa 2aa 55 555 a0 pa pd read ( 17 )1 00 data exit ( 17 ) 4 555 aa 2aa 55 555 90 xxx 00 legend: x = don?t care. ra = read address. rd = read data. pa = program address. addresses latch on the rising edge of the avd# pulse or active edge of clk, whichever occurs first. pd = program data. data latches on the rising edge of we# or ce# pulse, whichever occurs first. sa = sector address. ws256n = a23?a14; ws128n = a22?a14; ws064n = a21?a14. ba = bank address. ws256n = a23?a20; ws128n = a22?a20; ws064n = a21?a18. cr = configuration register data bits d15?d0. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 8.1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. 4. address and data bits not specifie d in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 5. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 6. no unlock or command cycles required when ba nk is reading array data. 7. reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autosele ct mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. the system must provide the bank address. see autoselect section for more information . 9. data in cycle 5 is 2230 (ws256n), 2232 (ws064n), or 2231 (ws128n). 10. see table 8.9 for indicator bit values. 11. total number of cycles in the command sequence is determined by the number of words written to the write buffer. 12. command sequence resets device for next command after write- to-buffer operation. 13. system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 14. erase resume command is valid only during the erase suspend mode, and requires the bank address. 15. command is valid when device is ready to read array data or when device is in autoselect mode. address equals 55h on all future devices, but 555h for ws256n/128n/064n. 16. requires entry command sequence prior to execution. unlock bypass reset command is required to return to reading array data. 17. requires entry command sequence prior to execution. secured silicon sector exit reset command is required to exit this mode; device may otherwise be placed in an unknown state. 18. requires reset command to configure the configuration register.
88 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 13.2 sector protection commands command sequence (notes) cycles bus cycles (notes 1 ? 4 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data lock register bits command set entry ( 5 ) 3 555 aa 2aa 55 555 40 program ( 6 , 12 ) 2 xx a0 77/00 data read ( 6 )1 77 data command set exit ( 7 ) 2 xx 90 xx 00 password protection command set entry ( 5 ) 3 555 aa 2aa 55 555 60 program [0-3] ( 8 ) 2 xx a0 00 pwd[0-3] read ( 9 )4 0...00 pwd0 0...01 pwd1 0...02 pwd2 0...03 pwd3 unlock 7 00 25 00 03 00 pwd0 01 pwd1 02 pwd2 03 pwd3 00 29 command set exit ( 7 ) 2 xx 90 xx 00 non-volatile sector protection (ppb) command set entry ( 5 ) 3 555 aa 2aa 55 [ba]555 c0 ppb program ( 10 ) 2 xx a0 sa 00 all ppb erase ( 10 , 11 ) 2 xx 80 00 30 ppb status read 1 sa rd(0) command set exit ( 7 ) 2 xx 90 xx 00 global volatile sector protection freeze (ppb lock) command set entry ( 5 ) 3 555 aa 2aa 55 [ba]555 50 ppb lock bit set 2 xx a0 xx 00 ppb lock bit status read 1 ba rd(0) command set exit ( 7 ) 2 xx 90 xx 00 volatile sector protection (dyb) command set entry ( 5 ) 3 555 aa 2aa 55 [ba]555 e0 dyb set 2 xx a0 sa 00 dyb clear 2 xx a0 sa 01 dyb status read 1 sa rd(0) command set exit ( 7 ) 2 xx 90 xx 00 legend: x = don?t care. ra = address of the memory location to be read. pd(0) = secured silicon sector lock bit. pd(0), or bit[0]. pd(1) = persistent protection mode lo ck bit. pd(1), or bit[1], must be set to ?0? for protection while pd(2), bit[2] must be left as ?1?. pd(2) = password protection mode lock bit. pd(2), or bit[2], must be set to ?0? for protection while pd(1), bit[1] must be left as ?1?. pd(3) = protection mode otp bit. pd(3) or bit[3]. sa = sector address. ws256n = a23?a14; ws 128n = a22?a14; ws064n = a21?a14. ba = bank address. ws256n = a23?a20; ws128n = a22?a20; ws064n = a21?a18. pwd3?pwd0 = password data. pd3?pd0 present four 16 bit combinations that represent the 64-bit password pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. rd(0), rd(1), rd(2) = dq0, dq1, or dq2 protection indicator bit. if protected, dq0, dq1, or dq2 = 0. if unprotected, dq0, dq1, dq2 = 1. notes: 1. all values are in hexadecimal. 2. shaded cells indicate read cycles. 3. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 4. writing incorrect address and data values or writ ing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 5. entry commands are required to en ter a specific mode to enable instructions only availa ble within that mode. 6. if both the persistent protection mode locking bit and the password protection mode locking bit are set at the same time, the command operation aborts and returns the device to the default persistent sector protection mode during 2nd bus cycle. note that on all future devices, addresses equal 00h, but is currently 77h for the ws256n only. see table 9.1 and table 9.2 for explanation of lock bits. 7. exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. entire two bus-cycle sequence must be entered for each portion of the password. 9. full address range is requ ired for reading password. 10. see figure 9.2 for details. 11. the all ppb erase command pre-progra ms all ppbs before erasure to prevent over-erasure. 12. the second cycle address for the lock register program operation is 77 for s29ws256n; however, for ws128n and ws064n this address is 00.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 89 advance information 13.1 common flash memory interface the common flash interface (cfi) specification outlines device and host system software inter- rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-indepen- dent, and forward- and back-ward-compatible fo r the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when th e system writes the cfi query command, 98h, to address (ba)555h any time the de vice is ready to read array data. the system can read cfi in- formation at the addresses given in tables 13.3?13.6 ) within that bank. all reads outside of the cfi address range, within the bank, returns non- valid data. reads from other banks are allowed, writes are not. to terminate reading cfi data, the system must write the reset command. the following is a c source code example of using the cfi entry and exit functions. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ for further information, please refer to the cfi specification (see jedec publications jep137-a and jesd68.01and cfi publication 100). please contact your sales office for copies of these documents. table 13.3 cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string qry 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 13.4 system interface string addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0006h typical timeout per single byte/word write 2 n s 20h 0009h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0004h max. timeout for buffer write 2 n times typical 25h 0003h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
90 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information ta b l e 1 3 . 5 device geometry definition addresses data description 27h 0019h (ws256n) 0018h (ws128n) 0017h (ws064n) device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0006h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0003h 0000h 0080h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 00fdh (ws256n) 007dh (ws128n) 003dh (ws064n) erase block region 2 information 32h 33h 34h 0000h 0000h 0002h 35h 36h 37h 38h 0003h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information table 13.6 primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major version number, ascii 44h 0034h minor version number, ascii 45h 0100h address sensitive unlock (bits 1-0), 0 = required, 1 = not required silicon technology (bits 5-2) 0100 = 0.11 m 46h 0002h erase suspend, 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect, 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 08 = advanced sector protection 4ah 00f3h (ws256n) 007bh (ws128n) 003fh (ws064n) simultaneous operation number of sectors in all banks except boot bank 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type, 00 = not supported, 01 = 4 word page, 02 = 8 word page, 04 = 16 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 0001h = dual boot device 50h 0001h program suspend. 00h = not supported
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 91 advance information 51h 0001h unlock bypass, 00 = not supported, 01=supported 52h 0007h secured silicon sector (customer otp area) size 2 n bytes 53h 0014h hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns 54h 0014h hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns 55h 0005h erase suspend time-out maximum 2 n ns 56h 0005h program suspend time-out maximum 2 n ns 57h 0010h bank organization: x = number of banks 58h 0013h (ws256n) 000bh (ws128n) 0007h (ws064n) bank 0 region information. x = number of sectors in bank 59h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 1 region information. x = number of sectors in bank 5ah 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 2 region information. x = number of sectors in bank 5bh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 3 region information. x = number of sectors in bank 5ch 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 4 region information. x = number of sectors in bank 5dh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 5 region information. x = number of sectors in bank 5eh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 6 region information. x = number of sectors in bank 5fh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 7 region information. x = number of sectors in bank 60h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 8 region information. x = number of sectors in bank 61h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 9 region information. x = number of sectors in bank 62h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 10 region information. x = number of sectors in bank 63h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 11 region information. x = number of sectors in bank 64h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 12 region information. x = number of sectors in bank 65h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 13 region information. x = number of sectors in bank 66h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 14 region information. x = number of sectors in bank 67h 0013h (ws256n) 000bh (ws128n) 0007h (ws064n) bank 15 region information. x = number of sectors in bank table 13.6 primary vendor-specific extended query (continued) addresses data description
92 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 14 commonly used terms te r m d e f i n i t i o n acc accelerate. a special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above v cc . in some devices acc may protect all sectors when at a low voltage. a max most significant bit of the address inpu t [a23 for 256mbit, a22 for128mbit, a21 for 64mbit] a min least significant bit of the address input si gnals (a0 for all devices in this document). asynchronous operation where signal relationships are ba sed only on propagation delays and are unrelated to synchronous control (clock) signal. autoselect read mode for obtaining manufacturer and device information as well as sector protection status. bank section of the memory array consisting of multiple consecutive sectors. a read operation in one bank, can be independen t of a program or erase operation in a different bank for devices that offer simultaneous read and write feature. boot sector smaller size sectors located at the top and or bottom of flash device address space. the smaller sector size allows for finer gra nularity control of erase and protection for code or parameters used to initiate system operation after power-on or reset. boundary location at the beginning or end of series of memory locations. burst read see synchronous read . byte 8 bits cfi common flash interface. a flash memory in dustry standard specification [jedec 137- a and jesd68.01] designed to allow a system to interrogate the flash to determine its size, type and other performance parameters. clear zero (logic low level) configuration register special purpose register which must be programmed to enable synchronous read mode continuous read synchronous method of burst read whereby the device reads continuously until it is stopped by the host, or it has reached the highest address of the memory array, after which the read address wraps around to the lowest memory array address erase returns bits of a flash memory array to th eir default state of a logical one (high level). erase suspend/erase resume halts an erase operation to allow reading or programming in any sector that is not selected for erasure bga ball grid array package. spansion llc offers two variations: fortified ball grid array and fine-pitch ball grid array. see the spec ific package drawing or connection diagram for further details. linear read synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with or without wraparound before requiring a new initial address . mcp multi-chip package. a method of combining in tegrated circuits in a single package by stacking multiple die of the same or different devices. memory array the programmable area of the product available for data storage. mirrorbit? technology spansion? trademarked technology for storin g multiple bits of data in the same transistor.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 93 advance information page group of words that may be accessed more ra pidly as a group than if the words were accessed individually. page read asynchronous read operation of several wo rds in which the first word of the group takes a longer initial access time and subsequent words in the group take less page access time to be read. different words in the group are accessed by changing only the least significan t address lines. password protection sector protection method wh ich uses a programmable passw ord, in addition to the persistent protection method , for protection of sectors in the flash memory device . persistent protection sector protection method that uses comm ands and only the standard core voltage supply to control protection of sectors in the flash memory device. this method replaces a prior technique of requiring a 12v supply to control th e protection method. program stores data into a flash memory by selectiv ely clearing bits of the memory array in order to leave a data pattern of ones and zeros . program suspend/program resume halts a programming operation to read data from any location that is not selected for programming or erase. read host bus cycle that causes the flash to output data onto the data bus. registers dynamic storage bits for holding device cont rol information or tracking the status of an operation. secured silicon secured silicon. an area co nsisting of 256 bytes in which any word may be programmed once, and the entire area ma y be protected once from any future programming. information in this area may be programmed at the factory or by the user. once programmed and protected ther e is no way to change the secured information. this area is often used to store a software readable identification such as a serial number. sector protection use of one or more control bi ts per sector to indicate whether each sector may be programmed or erased. if the protection bit for a sector is set the embedded algorithms for program or erase ignores program or erase commands related to that sector. sector an area of the memory array in which all bi ts must be erased together by an erase operation. simultaneous operation mode of operation in which a host system may issue a program or erase command to one bank, that embedded algorithm operat ion may then proceed while the host immediately follows the embedded algorith m command with reading from another bank. reading may continue concurrently in any bank other than the one executing the embedded algorithm operation. synchronous operation operation that progresses only when a timi ng signal, known as a clock, transitions between logic levels (that is, at a clock edge). versatileio? (v io ) separate power supply or voltage reference si gnal that allows the host system to set the voltage levels that the device genera tes at its data outputs and the voltages tolerated at its data inputs. unlock bypass mode that facilitates faster program time s by reducing the number of command bus cycles required to issue a write operation co mmand. in this mode th e initial two unlock write cycles, of the usual 4 cycle program command, are not required ? reducing all program commands to two bus cycles while in this mode. word two contiguous bytes (16 bits) located at an even byte boundary. a double word is two contiguous words located on a two word boundary. a quad word is four contiguous words located on a four word boundary. te r m d e f i n i t i o n
94 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information wraparound special burst read mode where the read address wraps or returns back to the lowest address boundary in the selected range of words, after reading the last byte or word in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read words in the sequence 2, 3, 0, 1. write interchangeable term for a program/erase operation where the content of a register and or memory location is being altered. the term write is often associated with writing command cycles to enter or exit a particular mode of operation. write buffer multi-word area in which multiple words may be programmed as a single operation . a write buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary respectively. write buffer programming method of writing multiple words, up to the maximum size of the write buffer, in one operation. using write buff er programming results in 8 times faster programming time than by using single word at a time programming commands. write operation status allows the host system to determine the status of a program or erase operation by reading several special purpose register bits . te r m d e f i n i t i o n
publication number s75ws-n-00 revision a amendment 0 issue date february 17, 2005 data sheet s29rs512n 512 megabit (32 m x 16-b it) cmos 1.8 volt-only read/write, burst mode, mass storage flash memory for multi-chip products (mcp) distinctive characteristics architectural advantages ? single 1.8 volt read, program and erase (1.65 to 1.95 volt) ? manufactured on 0.11 m mirrorbit tm process read/write operation ? zero latency between read and write operations ? programable burst interface ? 2 modes of burst read operation ? linear burst: 8, 16, and 32 words with or without wrap-around ? continuous sequential burst ? sector architecture ? one-hundred-twenty-eight 256 kword sectors ? 100,000 erase cycle per sector typical ? 20-year data retention typical performance charcteristics ? read access times at 80/66/54 mhz ? burst access times of 9.1/11.2/13.5 ns ? synchronous latency of 148 ns ? asynchronous random access times of 143 ns ? high performance ? typical word programming time of 40 s ? typical effective word programming time of 9.4 s utilizing a 32-word write buffer at vcc level ? typical effective word programming time of 6 s utilizing a 32-word write buffer at acc level ? typical 2 s sector erase time for 256 kword sectors ? power dissipation (typical values, c l = 30 pf) @ 80 mhz ? continuous burst mode read: 35 ma ? program: 19 ma ?erase: 19 ma ? standby mode: 20 a hardware features ? sector protection ? dynamic protection bits (dyb) are assigned to every sector ? a command sector protection to lock/unlock combinations of individual sectors to prevent/allow program or erase operatio ns within that sector. ? handshaking feature available ? provides host system with minimum possible latency by monitoring rdy ? acc input: acceleration function reduces programming time in a factory setting ? low v cc write inhibit software features ? software command set compatible with jedec 42.4 standards ? data# polling and toggle bits ? provides a software method of detecting program and erase operation completion ? erase suspend/resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? program suspend/resume ? suspends a programming operation to read data from a sector other than the on e being programmed, then resume the programming operation ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences additional features ? program operation ? ability to perform sync hronous and asynchronous write operation independent of burst control register setting
96 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet general description the s29rs512n is a 512 mbit, 1.8 volt-only, simultaneous read/write, burst mode flash memory device, organized as 33,554,432words of 16 bits each. this device uses a single v cc of 1.65 to 1.95 v to read, program, and erase the memory array. a 9.0-volt v hh on acc may be used for faster program performance in a factory setting environment. the device uses chip enable (ce#), write enab le (we#), address valid (avd#) and output en- able (oe#) to control asynchronous read and write operations. for burst operations, the device additionally requires ready (rdy), and clock (clk ). this implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. the burst read mode feature gives system designers flexibility in the interface to the device. the user can preset the burst length and then wrap or non-wrap through the same memory space, or read the currently addressable flas h array block in continuous mode. the rising clock edge initiates burst accesses and determines when data will be output. the device is entirely command set compatible with the jedec 42.4 single-power-supply flash standard . commands are written to the command register using standard microprocessor write timing. register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the em- bedded program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facilitates faster program times by requiring only two write cycles to program data instead of four. additionally, write buffer pro- gramming is available on this family of devices. this feature provides superior programming performance by grouping locations being programmed. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algorithm - an internal algorithm that automatically preprograms the array (if it is not al- ready programmed) before executing the erase oper ation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the program suspend/program resume feature enables the user to put program on hold to read data from any sector that is not selected for programming. if a read is needed from the dy- namic protection area after a program suspend, then the user must use the proper command sequence to enter and exit this region. the program suspend/resume functionality is also avail- able when programming in erase suspend (1 level depth only). the erase suspend/erase resume feature enables the user to put erase on hold to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the dynamic protection area, after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a sys- tem reset would thus also reset the device, enab ling the system microprocessor to read boot-up firmware from the flash memory device. the host system can detect whether a memory ar ray program or erase operation is complete by using the device status bit dq7 (data# polling) , dq6/dq2 (toggle bits), dq5 (exceeded timing limit), dq3 (sector erase start timeout state ind icator), and dq1 (write to buffer abort). after a program or erase cycle has been completed, the device automatically returns to reading array data.
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 97 data sheet the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors [the device is fully erased when shipped from the factory]. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. when the acc pin = v il , the entire flash memory array is protected. the device offers two power-savi ng features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes. spansion?s flash technology combines years of flash memory manufacturing experience to pro- duce the highest levels of quality, reliability and co st effectiveness. the device electrically erases all bits within a sector. the data is programmed using hot electron injection.
98 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 15 product selector guide s29rs512n synchronous/burst asynchronous speed option 80 mhz 66 mhz 54 mhz max latency, ns (t iacc ) 148 160 160 max access time, ns (t acc ) 143 max burst access time, ns (t bacc ) 9.1 11.2 13.5 max ce# access, ns (t ce ) 148 max oe# access, ns (t oe ) 9.1 11.2 13.5 max oe# access, ns (t oe )9.1
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 99 data sheet 16 block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# reset# acc ce# oe# dq15 ? dq0 data latch y-gating cell matrix address latch amax?a0* rdy buffer rdy burst state control burst address counter avd# clk amax = a24
100 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 17 logic symbol note: amax = a24 for 512mb. 25 or 24 16 dq15?dq0 amax? ce# oe# we# reset# clk rdy avd# acc
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 101 data sheet 18 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addres- sable memory location. the register is composed of latches that store the commands, along with the address and data information needed to exec ute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 1 8 . 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 18.1 device bus operations legend: l = logic 0, h = logic 1, x = don?t care. 18.1 requirements for asynchronous read operation (non-burst) to read data from the memory array, the system must first assert a valid address on amax?a0, while driving avd# and ce# to v il . we# should remain at v ih . the rising edge of avd# latches the address. the data will appear on dq15?dq0. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling ed ge of oe# to valid data at the output. the internal state machine is set for reading ar ray data in asynchrono us mode upon device power-up, or after a hardware rese t. this ensures that no spurious alteration of the memory con- tent occurs during the power transition. operation ce# oe# we# addresses dq15?0 reset# clk avd# asynchronous read - addresses latched l l h addr in i/o h x asynchronous read - addresses steady state l l h addr in i/o h x l asynchronous write l h l addr in i/o h x l synchronous write l h l addr in i/o h standby (ce#) h x x x high z h x x hardware reset x x x x high z l x x burst read operations load starting burst address l x h addr in x h advance burst to next address with appropriate data presented on the data bus llh x burst data out hh terminate current burst read cycle h x h x high z h x terminate current burst read cycle via reset# x x h x high z l x x terminate current burst read cycle and start new burst read cycle l x h addr in i/o h
102 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 18.2 requirements for synchronous (burst) read operation the device is capable of continuous sequential bu rst operation and linear burst operation of a pre- set length. when the device first powers up, it is enabled for asynchronous read operation. prior to entering burst mode, the system should determine how many wait states are desired for the initial word (t iacc ) of each burst access, what mode of burst operation is desired and how the rdy signal will transition with valid data. the syst em would then write the configuration register command sequence. see set configuration register command sequence for further details. table 2-4 shows the address latency scheme for varying frequencies. address latency scheme for < 84mhz the initial word is output t iacc after the rising edge of the first clk cycle. subsequent words are output t bacc after the rising edge of each successive clock cycle, which automatically increments the internal address counter. note that the device has a fixed internal address boundary that oc- curs every 512 words and there is a boundary crossing latency of 4/8 wait states, when the device is operating at frequencies lower than 56/80mhz respectively. during the time the device is outputting data with the starting burst address not divisible by four, additional waits are required. for example, if th e device is operating at frequency of 80mhz and if the starting burst address is divisible by four a1:0 = 00, two additional wait state is required. table 18.2 address latency scheme for < 56mhz initial addr cycle x x+1 x+2 x+3 add ws x+4 x+5 x+6 00 d0 d1 d2 d3 0ws d4 d5 d6 01 d1 d2 d3 1ws 0ws d4 d5 d6 10 d2 d3 1ws 1ws 0ws d4 d5 d6 11 d3 1ws 1ws 1ws 0ws d4 d5 d6 table 18.3 address latency scheme for < 70mhz initial addr cycle x x+1 x+2 x+3 add ws x+4 x+5 x+6 00 d0 d1 d2 d3 1ws d4 d5 d6 01 d1 d2 d3 1ws 1ws d4 d5 d6 10 d2 d3 1ws 1ws 1ws d4 d5 d6 11 d3 1ws 1ws 1ws 1ws d4 d5 d6 table 18.4 address latency scheme for < 84mhz initial addrs cycle x x+1 x+2 x+3 add ws x+4 x+5 x+6 00 d0 d1 d2 d3 2ws d4 d5 d6 01 d1 d2 d3 1ws 2ws d4 d5 d6 10 d2 d3 1ws 1ws 2ws d4 d5 d6 11 d3 1ws 1ws 1ws 2ws d4 d5 d6
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 103 data sheet if the starting burst address is at address a1:0 = 01, 10, 11 then three, four or five wait states are required, respectively, until data d4 is read and burst sequence becomes linear. please refer to table 18.4 for further details. the rdy output indicates this condition to the system by deasserting. 18.2.1 continuous burst the device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives ce# high, re- set# low, or avd# low in conjunction with a new address. see ta b l e 1 8 . 1 . 18.2.2 8-, 16-, and 32-word linear burst with wrap around the remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burst addresses read are determined by the group within which the star ting address falls. the groups are sized accord- ing to the number of words read in a singl e burst sequence for a given mode (see ta b l e 1 8 . 5 .). as an example: if the starting address in the 8- word mode is 3ch, the address range to be read would be 38-3fh, and the burst sequence would be 3c, 3d, 3e, 3f, 38, 39, 3a, 3bh. if wrap around is enable. the burst sequence begins with the st arting address written to the device, but wraps back to the first address in the selected group and stops at the group size, terminating the burst read. in a similar fashion, the 16-word and 32- word linear wrap modes begin their burst se- quence on the starting address written to the devi ce, and then wrap back to the first address in the selected address group. note that in these three burst read modes the address pointer does not cross the boundary that occurs ever y 512 words; thus, no wait states are in- serted (except during the initial access). (see figure 25.4 ) 18.2.3 8-, 16-, and 32-word linear burst without wrap around if wrap around is not enabled, 8-word, 16-word, or 32-word burst will execute linearly up to word boundary. the burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address of the selected group. as an example: if the starting address in the 8-word mode is 3ch, the address range to be read would be 39-40h, and the burst sequence would be 3c, 3d-3e-3f- 40-41-42-43h if wrap around is not enabled. the next address to be read will require a new ad- dress and avd# pulse. the address range would stay within the address block, causing address ffffh to be followed by 0000h. note that in this burst mode, the address pointer may cross the boundary that occurs every 128 words. 18.3 configuration register the device uses a configuration register to se t the various burst parameters: number of wait states, burst read mode, rdy configuration, and synchronous mode active. 18.4 rdy: ready the rdy is a dedicated output that, when the device is configured in the synchronous mode, in- dicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. the rdy pin is only controlled by ce#. using the rdy configuration command sequence, rdy can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. table 18.5 burst address groups mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h,... 16-word 16 words 0-fh, 10-1fh, 20-2fh,... 32-word 32 words 00-1fh, 20-3fh, 40-5fh,...
104 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet the following conditions cause the rdy output to be low: during the initial access (in burst mode), and at the boundary crossing, that occurs ev ery 512 words beginning with address 1ffh. 18.5 handshaking the device is equipped with a handshaking feature that allows the host system to simply monitor the rdy signal from the device to determine when the burst data is ready to be read. the host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. the initial word of burst data is indicated by the rising edge of rdy after oe# goes low. for optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on clock frequency. see set configuration register command sequence and requirements for synchronous (burst) read operation for more information. 18.6 writing commands/command sequences the device has the capability of performing an asynchronous or synchronous write operation. while the device is configured in asynchronous read it is able to perform asynchronous write op- erations only. clk is ignored when the device is configured in the asynchronous mode. when in the synchronous read mode configuration, the device is able to perform both asynchronous and synchronous write operations. clk and avd# addr ess latch is supported in the synchronous pro- gramming mode. during a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the de- vice, and drive we# and ce# to v il , and oe# to v ih . when writing commands or data. during an asynchronous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresse s are latched on the last falling edge of we# or ce#, while data is latched on the 1s t rising edge of we# or ce# (see ). the device features an unlock bypass mode to facilitate faster programming. once the device en- ters the unlock bypass mode, only two write cycles are required to program a word, instead of four. an erase operation can erase one sector, multiple sectors or the entire device. ta b l e 1 9 . 6 indicates the address space that each sector occupies. a sector address is the address bits required to uniquely select a sector. i cc2 in the dc characteristics section represents the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. 18.7 accelerated program/chip erase operations the device offers accelerated program and accelerated chip erase operations through the acc functionacc is intended to allow faster manufactu ring throughput at the factory and not to be used in system operations. the system can use the write buffer load command sequence. note that if a write-to-buffer- abort reset is required, the full 3-cycle reset command sequence must be used to reset the device . removing v hh from the acc input, upon completion of the embedded program or erase operation, returns the device to normal oper ation. note that sectors must be unlocked prior to raising acc to v hh . when at v il , acc locks all sectors. acc should be at v ih for all other conditions. number loaded = the number of locations to program minus 1. for example, if the system will program 6 address locations, then 05h should be written to the device.)
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 105 data sheet the system then writes the starting address/data combination. this starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. all subsequent address/data pairs must fall within the selected-write-buffer-page where amax = 24 for rs512n. the write-buffer-page is selected by addresses amax - a5. the write-buffer-page addresses must be the same for all addr ess/data pairs loaded into the write buffer . (this means write buffer programming cannot be performed across multiple write-buffer-page s. this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected write- buffer-page , the operation will abort.) after writing the starting address/data pair, the system then writes the remaining address/data paris into the write buffer. write buffer locations may be loaded in any order. note that if a write buffer address location is loaded multiple times, the address/data pair counter will be decremented for ev ery data load operation . also, the last data loaded at a location before the program buffer to flash confirm command will be programmed into the device. it is the software?s responsibility to comprehend ramifications of loading a write-buffer location more than once. the counter decrements for each data load operation , not for each unique write- buffer-address location . once the specified number of write buffer location s have been loaded, the system must then write the program buffer to flash command at the sector address. any other address/data write com- binations will abort the write buffer programming operation. the device then goes busy . the data bar polling techniques should be used while monitoring the last address location loaded into the write buffer . this eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same a ddress. dq7, dq6, dq5, dq2, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer embedded programming operation can be suspended using the standard sus- pend/resume commands. upon successful completion of the write buffer programming operation, the device will return to read mode. the write buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to pro- gram step. ? write to an address in a sector differe nt than the one specified during the write-buffer-load command. ? write an address/data pair to a different wr ite-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded ), dq6 = toggle, dq5 = 0. this indicates that the write buffer programming operation was aborted. a write-to-buffer-abort reset command sequence is required when using the write- buffer-programming features in unlock bypass mode. [use of the write buffer is strongly rec- ommended for programming when mult iple words are to be programmed.] from the internal register (which is separate from the memory array) 18.8 dynamic sector protection the device offers data protection at the sector level and the dyb associated command sequences disables or re-enables both program and erase operations in any sector or sector group. ? dynamically locked?the sector is protected and can be changed by a simple command ? unlocked?the sector is unprotected an d can be changed by a simple command
106 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 18.8.1 dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the con- tents of all dybs is cleared erased to 1 . in other words, the dyb po wers-up in an unprotected state. each dyb is individually modifiable through the dyb write command. the protection state for each sector is determin ed by the dyb related to that sector. the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write com- mand sequences, the dybs will be set (programmed to 0 ) or cleared (erased to 1 ), thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dybs maybe set or cleared as often as needed. 18.9 standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is grea tly reduced, and the outputs are placed in the high impedance state, inde pendent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc . the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in the dc characteristics section represents the standby current specification. 18.10 automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. while in asynchronous mode, the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. stan- dard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. while in synchronous mode, the auto- matic sleep mode is disabled. note that a new bu rst operation is required to provide new data. i cc6 in the dc characteristics section represents the automatic sleep mode current specification. 18.11 reset#: hardware reset input the reset# input provides a hard ware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss , the standby cur- rent will be greater. reset# may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted t rp operation, the device requires a time of t rh + t rp before the device is ready to read data again. if reset# is asserted when a program or erase operation is not exe- cuting, the reset operation is completed within a time of t rp (not during embedded algorithms). the system can read data t rh after reset# returns to v ih .
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 107 data sheet refer to the synchronous/burst read section for reset# parameters and to figure 25.9 for the timing diagram. 18.12 output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. 18.13 hardware data protection the following hardware data prot ection measures prevent accide ntal erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. 18.13.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any writ e cycles. this prot ects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . 18.13.2 write pulse glitch protection noise pulses do not initiate a write cycle. 18.13.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one.
108 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 19 sector address / memory address map table 19.6 sector address / memory address map for the rs512n sector sector size (a24-a0) address range sector sector size (a24-a0) address range sa0 256 kwords 0000000h-003ffffh sa64 256 kwords 1000000h-103ffffh sa1 256 kwords 0040000h-007ffffh sa65 256 kwords 1040000h-107ffffh sa2 256 kwords 0080000h-00bffffh sa66 256 kwords 1080000h-10bffffh sa3 256 kwords 00c0000h-00fffffh s a67 256 kwords 10c0000h-10fffffh sa4 256 kwords 0100000h-013ffffh sa68 256 kwords 1100000h-113ffffh sa5 256 kwords 0140000h-017ffffh sa69 256 kwords 1140000h-117ffffh sa6 256 kwords 0180000h-01bffffh sa70 256 kwords 1180000h-11bffffh sa7 256 kwords 01c0000h-01fffffh s a71 256 kwords 11c0000h-11fffffh sa8 256 kwords 0200000h-023ffffh sa72 256 kwords 1200000h-123ffffh sa9 256 kwords 0240000h-027ffffh sa73 256 kwords 1240000h-127ffffh sa10 256 kwords 0280000h-02bffffh sa74 256 kwords 1280000h-12bffffh sa11 256 kwords 02c0000h-02fffffh s a75 256 kwords 12c0000h-12fffffh sa12 256 kwords 0300000h-033ffffh sa76 256 kwords 1300000h-133ffffh sa13 256 kwords 0340000h-037ffffh sa77 256 kwords 1340000h-137ffffh sa14 256 kwords 0380000h-03bffffh sa78 256 kwords 1380000h-13bffffh sa15 256 kwords 03c0000h-03fffffh s a79 256 kwords 13c0000h-13fffffh sa16 256 kwords 0400000h-043ffffh sa80 256 kwords 1400000h-143ffffh sa17 256 kwords 0440000h-047ffffh sa81 256 kwords 1440000h-147ffffh sa18 256 kwords 0480000h-04bffffh sa82 256 kwords 1480000h-14bffffh sa19 256 kwords 04c0000h-04fffffh s a83 256 kwords 14c0000h-14fffffh sa20 256 kwords 0500000h-053ffffh sa84 256 kwords 1500000h-153ffffh sa21 256 kwords 0540000h-057ffffh sa85 256 kwords 1540000h-157ffffh sa22 256 kwords 0580000h-05bffffh sa86 256 kwords 1580000h-15bffffh sa23 256 kwords 05c0000h-05fffffh s a87 256 kwords 15c0000h-15fffffh sa24 256 kwords 0600000h-063ffffh sa88 256 kwords 1600000h-163ffffh sa25 256 kwords 0640000h-067ffffh sa89 256 kwords 1640000h-167ffffh sa26 256 kwords 0680000h-06bffffh sa90 256 kwords 1680000h-16bffffh sa27 256 kwords 06c0000h-06fffffh s a91 256 kwords 16c0000h-16fffffh sa28 256 kwords 0700000h-073ffffh sa92 256 kwords 1700000h-173ffffh sa29 256 kwords 0740000h-077ffffh sa93 256 kwords 1740000h-177ffffh sa30 256 kwords 0780000h-07bffffh sa94 256 kwords 1780000h-17bffffh sa31 256 kwords 07c0000h-07fffffh s a95 256 kwords 17c0000h-17fffffh sa32 256 kwords 0800000h-083ffffh sa96 256 kwords 1800000h-183ffffh sa33 256 kwords 0840000h-087ffffh sa97 256 kwords 1840000h-187ffffh sa34 256 kwords 0880000h-08bffffh sa98 256 kwords 1880000h-18bffffh sa35 256 kwords 08c0000h-08fffffh s a99 256 kwords 18c0000h-18fffffh sa36 256 kwords 0900000h-093ffffh sa100 256 kwords 1900000h-193ffffh sa37 256 kwords 0940000h-097ffffh sa101 256 kwords 1940000h-197ffffh sa38 256 kwords 0980000h-09bffffh sa102 256 kwords 1980000h-19bffffh sa39 256 kwords 09c0000h-09fffffh s a103 256 kwords 19c0000h-19fffffh
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 109 data sheet 19.1 reading array data the device is automatically set to reading arra y data after device po wer-up. no commands are required to retrieve data in asynchronous mode. the device is ready to read array data after com- pleting an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same device. after completing a programming op eration in the erase suspend mode, the system may once again read array data from any non-erase-suspended sector within the same device. see the erase suspend/erase resume commands section for more information. after the device accepts a program suspend co mmand, the device enters the program-suspend- read mode, after which the system can read data from any non-program-suspended sector within the device. see program suspend/program resume commands for more information. the system must issue the reset command to retu rn device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the au- toselect mode. see the reset command section for more information. if dq1 goes high during write buffer programming, the system must issue the write buffer abort reset command. sa40 256 kwords 0a00000h-0a3ffffh sa104 256 kwords 1a00000h-1a3ffffh sa41 256 kwords 0a40000h-0a7ffffh sa105 256 kwords 1a40000h-1a7ffffh sa42 256 kwords 0a80000h-0abffffh sa106 256 kwords 1a80000h-1abffffh sa43 256 kwords 0ac0000h-0afffffh s a107 256 kwords 1ac0000h-1afffffh sa44 256 kwords 0b00000h-0b3ffffh sa108 256 kwords 1b00000h-1b3ffffh sa45 256 kwords 0b40000h-0b7ffffh sa109 256 kwords 1b40000h-1b7ffffh sa46 256 kwords 0b80000h-0bbffffh sa110 256 kwords 1b80000h-1bbffffh sa47 256 kwords 0bc0000h-0bfffffh sa111 256 kwords 1bc0000h-1bfffffh sa48 256 kwords 0c00000h-0c3ffffh sa112 256 kwords 1c00000h-1c3ffffh sa49 256 kwords 0c40000h-0c7ffffh sa113 256 kwords 1c40000h-1c7ffffh sa50 256 kwords 0c80000h-0cbffffh sa114 256 kwords 1c80000h-1cbffffh sa51 256 kwords 0cc0000h-0cfffffh sa115 256 kwords 1cc0000h-1cfffffh sa52 256 kwords 0d00000h-0d3ffffh sa116 256 kwords 1d00000h-1d3ffffh sa53 256 kwords 0d40000h-0d7ffffh sa117 256 kwords 1d40000h-1d7ffffh sa54 256 kwords 0d80000h-0dbffffh sa118 256 kwords 1d80000h-1dbffffh sa55 256 kwords 0dc0000h-0dfffffh sa119 256 kwords 1dc0000h-1dfffffh sa56 256 kwords 0e00000h-0e3ffffh sa120 256 kwords 1e00000h-1e3ffffh sa57 256 kwords 0e40000h-0e7ffffh sa121 256 kwords 1e40000h-1e7ffffh sa58 256 kwords 0e80000h-0ebffffh sa122 256 kwords 1e80000h-1ebffffh sa59 256 kwords 0ec0000h-0efffffh s a123 256 kwords 1ec0000h-1efffffh sa60 256 kwords 0f00000h-0f3ffffh sa124 256 kwords 1f00000h-1f3ffffh sa61 256 kwords 0f40000h-0f7ffffh sa125 256 kwords 1f40000h-1f7ffffh sa62 256 kwords 0f80000h-0fbffffh sa126 256 kwords 1f80000h-1fbffffh sa63 256 kwords 0fc0000h-0ffffffh sa127 256 kwords 1fc0000h-1ffffffh table 19.6 sector address / memory address map for the rs512n (continued) sector sector size (a24-a0) address range sector sector size (a24-a0) address range
110 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet see also the requirements for asynchronous read operation (non-burst) and the requirements for synchronous (burst) read operation sections for more information. the asynchronous read and synchronous/burst read tables provide the read parameters, figure 25.2 , figure 25.3 , and figure 25.7 show the timings. 19.2 set configuration register command sequence the device uses a configuration register to se t the various burst parameters: number of wait states, burst read mode, rdy configuration, and synchronous mode active. the configuration reg- ister must be set before the device will enter burst mode. the configuration register is loaded with a four-c ycle command sequence. the first two cycles are standard unlock sequences. on the third cycle, the data should be d0h and address bits should be 555h. during the fourth cycle, the configuratio n code should be entered onto the data bus with the address bus set to address 000h or 001h. on ce the data has been programmed into the con- figuration register, a software reset command is required to set the device into the correct state. the device will power up or after a hardware reset with the default setting, which is in asynchro- nous mode. the register must be set before the device can enter synchronous mode. the configuration register can not be changed during device operations (program, erase, or sector lock). 19.3 read configuration register command sequence the configuration register can be read with a four-cycle command sequence. the first two cycles are standard unlock sequences. on the third cycl e, the data should be c6h and address bits should be 555h. during the fourth cycle, the configuration code should be read out of the data bus with the address bus set to address 000h or 001h. once the data has been read from the configuration register, a software reset command is required to set the device into array read mode. figure 19.1 synchronous/asynchronous state diagram power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (d15 = 0) set burst mode configuration register command for asynchronous mode (d15 = 1)
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 111 data sheet 19.3.1 read mode setting on power-up or hardware reset, the device is set to be in asynchronous read mode. this setting allows the system to enable or disable burst mode during system operations. configuration bit cr0.15 determines this setting: 1 for asynchronous mode, 0 for synchronous mode. 19.3.2 programmable wait state configuration the programmable wait state feature informs the device of the number of clock cycles that must elapse after avd# is driven active before data will be available. this value is determined by the input frequency of the device. configuration bit cr1.0 & cr0.13?cr0.11 determine the set- ting (see ta b l e 1 9 . 7 ). the wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. the number of wait states that should be programmed into the device is directly related to the clock frequency. notes: 1. upon power-up or hardware reset, the default setting is twelve wait states. 2. all other but setting are reserved. it is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is se t as expected. a hardware reset will set the wait state to the default setting. 19.3.3 programmable wait state the host system should set cr1.0 & cr 0.13-cr0.11 to 1100/1010/1000 for a clock frequency of 80/66/54 mhz for the system/device to execute at maximum speed. 19.3.4 boundary crossing latency additional wait states must be inserted to account for boundary crossing latency. this is done by setting cr0.14 to a ?1? (default). if required, cr0.14 can be changed to a ?0? to remove the boundary crossing latency. table 19.7 programmable wait state settings cr1.0 cr0.13 cr0.12 cr0.11 total initial access cycles 00 0 0 reserved 00 0 1 3 00 1 0 4 00 1 1 5 01 0 0 6 01 0 1 7 01 1 0 reserved 01 1 1 reserved 10 0 0 8 10 0 1 9 10 1 0 10 10 1 1 11 1 1 0 0 12 (default) 11 0 1 13 11 1 0 reserved 11 1 1 reserved
112 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 19.3.5 handshaking for optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. the autoselect function allows the host system to determine whether the flash device is enabled for handshaking. see the autoselect command sequence for more information. 19.3.6 burst length configuration the device supports four different read modes: co ntinuous mode, and 8, 16, and 32 word linear with or without wrap around modes. a continuous sequence (default) begins at the starting ad- dress and advances the address pointer until the burst operation is complete. if the highest address in the device is reached during the co ntinuous burst read mode, the address pointer wraps around to the lowest address. for example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. the address pointer then returns to the 1st word after the previous eight word bo undary, wrapping through the starting location. the sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight- word mode. table 19.8 shows the cr0.2-cr0.0 and settings for the four read modes. note: upon power-up or hardware reset the default setting is continuous. 19.3.7 burst wrap around by default, the device will perform burst wrap around with cr0.3 set to a ?1?. changing the cr0.3 to a ?0? disables burst wrap around. 19.3.8 rdy configuration by default, the device is set so that the rdy pin will output v oh whenever there is valid data on the outputs. the device can be set so that rdy goes active one data cycle before active data. cr0.8 determines this setting; 1 for rdy active (default) with data, 0 for rdy active one clock cycle before valid data. 19.3.9 rdy polarity by default, the rdy pin will always indicate that the device is ready to handle a new transaction with cr0.10 set to a ?1?. in this case, the rdy pin is active high. changing the cr0.10 to a ?0? sets the rdy pin to be active low. in this case, the rdy pin will always indicate that the device is ready to handle a new transaction when low. table 19.8 burst length configuration burst modes address bits cr0.2 cr0.1 cr0.0 continuous 0 0 0 8-word linear 0 1 0 16-word linear 0 1 1 32-word linear 1 0 0
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 113 data sheet 19.4 configuration register table 19.9 shows the address bits that determine the configuration register settings for various device functions. note: 3.device will be in the default state upon power-up or hardware reset. table 19.9 configuration register cr0. bit function settings (binary) cr0.15 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous mode (default) cr0.14 boundary crossing 0 = no extra boundary crossing latency 1 = with extra boundary crossing latency (default) cr1.0 programmable wait state 0000 = reserved 0001 = data is valid on the 4th active clk edge after addresses are latched 0010 = data is valid on the 5th active clk edge after addresses are latched 0011 = data is valid on the 6th active clk edge after addresses are latched 0100 = data is valid on the 7th active clk edge after addresses are latched 0101 = data is valid on the 8th active clk edge after addresses are latched 0110 = reserved 0111 = reserved 1000 = data is valid on the 9th active clk edge after addresses are latched 1001 = data is valid on the 10th active clk edge after addresses are latched 1010 = data is valid on the 11th active clk edge after addresses are latched 1011 = data is valid on the 12th active clk edge after addresses are latched 1100 = data is valid on the 13th active clk edge after addresses are latched (default) 1101 = data is valid on the 14th active clk edge after addresses are latched 1110 = reserved 1111 = reserved cr0.13 cr0.12 cr0.11 cr0.10 rdy polarity 0 = rdy signal is active low 1 = rdy signal is active high (default) cr0.9 reserved 1 = default cr0.8 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) cr0.7 reserved 1 = default cr0.6 reserved 1 = default cr0.5 reserved 0 = default cr0.4 reserved 0 = default cr0.3 burst wrap around 0 = no wrap around burst 1 = wrap around burst (default) cr0.2 burst length 000 = continuous (default) 010 = 8-word linear burst 011 = 16-word linear burst 100 = 32-word linear burst (all other bit settings are reserved) cr0.1 cr0.0
114 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 19.5 reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to which the system was writing to the read mode. [once erasure begins, however, the device ig nores reset commands until the operation is complete]. the reset command may be writ ten between the sequence cycles in a program command se- quence before programming begins (prior to the third cycle). this resets the device to which the system was writing to the read mode. if the program command sequence is written to the device that is in the erase suspend mode, writing the reset command returns the device to the erase- suspend-read mode. once progra mming begins, however, the de vice ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command se- quence. once in the autoselect mode, the reset command must be written to return to the read mode. if a device entered the autoselect mode while in the erase suspend mode, writing the reset command returns that device to the erase-suspend-read mode. if dq5 goes high during a program or erase op eration, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend and program-suspend-read mode if the device was in program suspend). note: if dq1 goes high during a write buff er programming operation, the system must write the write to buffer abort reset command sequence to reset the device to read- ing array data. the standard reset command will not work. see table 19.9 for details on this command sequence. 19.6 autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. the autoselect command sequence may be written to an ad- dress within the device that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autosele ct command. the device then enters the autose- lect mode. no subsequent data will be made available if the autoselect data is read in synchronous mode. the system may read at any address within the device any number of times without initi- ating another autoselect command sequence. the following table describes the address requirements for the various autoselect functions, and the resulting data. the device id is read in three cycles. table 19.10 autoselect addresses description address read data manufacturer id 00h 01h device id, word 1 01h 227eh device id, word 2 0eh 2229 (rs512n) device id, word 3 0fh 2201 (rs512n) indicator bits 03h dq15 - dq5 = 0 dq4 & dq3 = 11 dq2 - dq0 = 0
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 115 data sheet the system must write the reset command to retu rn to the read mode (or erase-suspend-read mode if the device was previously in erase suspend). 19.7 program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writ- ing two unlock write cycles, followed by the pr ogram set-up command. th e program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally gen- erated program pulses and verifies the programmed cell margin. the command definitions table shows the address and data requirements for the program command sequence. when the embedded program algorithm is complete , the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program oper- ation by monitoring dq7 or dq6/dq2. refer to the ?write operation status? section for information on these status bits. any commands written to the device during the embedded program algori thm are ignored. note that a hardware reset immediately terminates the program operation. the program command se- quence should be reinit iated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be pro- grammed from 0 back to a 1 . only erase operations can convert a 0 back to a 1 . attempting to program a 1 over a 0 will result in a programming failure. note: see the command definitions table for program command sequence. figure 19.2 program word operation 19.8 write buffer programming command sequence write buffer programming sequence allows for faster programming as compared to the standard program command sequence. see the write buffer programming operation section for the pro- gram command sequence. table 19.11 write buffer command sequence sequence address data comment unlock command 1 555 00aa not requir ed in the unlock bypass mode unlock command 2 2aa 0055 same as above write buffer load sector address 0025h specify the number of program locations starting address word count number of locations to program minus 1 load 1st data word starting address program data all addresses must be within write-buffer- page boundaries, but do not have to be loaded in any order load next data word write buffer location program data same as above ... ... ... same as above load last data word write buffer location program data same as above write buffer program confirm sector address 0029h this command must follow the last write buffer location loaded, or the operation will abort device goes busy status monitoring through dq pins (perform data bar polling on the last loaded address )
116 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet figure 19.3 write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1 and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq15 - dq0 at last loaded address read dq15 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode.
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 117 data sheet 19.8.1 unlock bypass command sequence the unlock bypass feature allows the system to primarily program to the device faster than using the standard word program command sequence. the unlock bypass command sequence is initi- ated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock by- pass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pr ogram command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. during the unlock bypass mode, only the unlock bypass program command is valid. to exit the unlock bypass mode, the system must issue th e two-cycle unlock bypass reset command se- quence. the first cycle must contain the data 90h. the second cycle need only contain the data 00h. the device then re turns to the read mode. 19.9 chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in tu rn invokes the embedded erase algorithm. the device does not require the system to preprogr am prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these oper- ations. the command definitions table shows the address and da ta requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and ad- dresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to the write operation status section for information on these sta- tus bits. any commands written during the chip erase op eration are ignored. however, note that a hard- ware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 20.4 illustrates the algorithm for the erase operation. refer to the erase/program opera- tions table in the ac characteristics section for parameters and timing diagrams. 19.10 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writ- ing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sect or to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than 50 s occurs. during the time-out period, additional sector addresses and sector erase commands may be writ- ten. loading the sector erase buffer may be do ne in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than
118 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet t sea . any sector erase address and command following the exceeded time-out may or may not be accepted. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system can monitor dq3 to determine if the sector erase timer has timed out (see dq3: sec- tor erase timer .) the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7 or dq6/dq2. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a ha rdware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the de- vice has returned to reading array data, to ensure data integrity. figure 20.4 illustrates the algorithm for the erase operation. refer to the erase/program opera- tions table in the erase/program operations section for parameters and timing diagrams. 19.10.1 accelerated sector erase under certain conditions, the device can erase sectors in parallel. this method of erasing sectors is faster than the standard sector erase command sequence. ta b l e 1 9 . 6 lists the sectors. the accelerated sector erase f unction must not be used more than 100 times per sector. in addition, accelerated sector erase should be performed at room temperature 30 c (+/-) 5 c. use the following procedure to perform accelerated sector erase: 1. unlock all sectors in a sector to be erased using the sector lock/unlock command sequence. all sectors that remain locked will not be erased. 2. apply 9 v to the acc input. this voltage must be applied at least 1 s before executing step 3 . 3. write 80h to any address within a sector to be erased. 4. write 30h to any address within a sector to be erased. 5. monitor status bits dq2/dq6 or dq7 to determ ine when erasure is complete, just as in the standard erase operation. see the write operation status section for further details. 6. lower acc from 9 v to v cc . 7. relock sectors as required.
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 119 data sheet 20 erase suspend/erase resume commands notes: 1.see the command definitions table for erase command sequence. 2.see the section on dq3 for information on the sector erase timer. figure 20.4 erase operation the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the minimum t sea time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device re- quires a maximum of t esl (erase suspend latency) to susp end the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device imme- diately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the de- vice erase suspends all sectors selected for erasure.) reading at any address within erase- suspended sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status for information on these status bits. after an erase-suspended program operation is complete, the device returns to the erase-sus- pend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. see write buffer programming operation and autoselect command sequence for details. to re- sume the sector erase operation, the system must write the erase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. 20.1 program suspend/program resume commands the program suspend command allows the system to interrupt a embedded programming oper- ation or a write to buffer programming operation so that data can read from any non-suspended sector. when the program suspend command is written during a programming process, the de- vice halts the programming operation within t psl (program suspend latency) and updates the status bits. addresses are don?t-cares when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a program- ming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secsi sector area (one time program area), then user must use the pr oper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in pro- gram suspend mode. the device allows reading au toselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information.
120 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet after the program resume command is written, the device reverts to programming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the system must write the program resume command (address bits are don?t care ) to exit the program sus- pend mode and continue the pr ogramming operation. further writes of the program resume command are ignored. another program suspend command can be written after the device has resume programming. 20.2 volatile sector protection command set the volatile sector protection command set permits the user to set the dynamic protection bit (dyb), clear the dynamic protection bit (dyb), and read the logic state of the dynamic protection bit (dyb). the volatile sector protec tion command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the volatile sector protection command set entry command disables reads and writes for the device with the command. ? dyb set command ? dyb clear command ? dyb status read command the dyb set/clear command is used to set or cl ear a dyb for a given se ctor. the address bits are issued at the same time as the code 00h or 01h on dq7-dq0. all othe r dq data bus pins are ignored during the data write cycle. the dybs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. the dybs are cleared (erased to ?1?) at power-up or hardware reset and are thus in an unprotected state. the programming state of the dyb for a given sector can be verified by writing a dyb status read command to the device. the volatile sector protection command set exit command must be issued after the execu- tion of the commands listed previously to reset the device to read mode. otherwise the device will hang. note that issuing the volatile sector protection command set exit command re-enables reads and writes for the device.
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 121 data sheet 21 command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses la tch on the rising edge of the avd# pulse or active edge of cl k which ever comes first. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a24?a14 for the rs512n uniquely select a ny sector. cr = configuration register data bits d15?d0. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 18.1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the autoselect commands, fourth cycle of the configuration register verify command, and any cycle reading at rd(0) and rd(1). 4. data bits dq15?dq8 are don?t care in comm and sequences, except for rd, pd, and wd. 5. unless otherwise noted, address bits amax?a12 are don?t cares. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when device is reading array data. 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspe nd) when device is in the autoselect mode, or if dq 5 goes high (while the device is providing status information) or performing sector l ock/unlock. 9. the fourth cycle of the autoselect command sequence is a read cycle. see the autoselect command sequence section. 10. 512 mb: 0eh = 29h and 0fh = 01h. 11. see the autoselect command sequence section. 12. the unlock bypass command sequence is required prior to this command sequence. 13. the unlock bypass reset command is required to return to read ing array data when the device is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation. 15. the erase resume command is valid only during the erase suspend mode 16. see the set configuration register command sequence section. 17. see the read configuration register command sequence section which further provides information on reset command to configure the configuration register. 18. the total number of cycles in the command sequence is determin ed by the number of words written to the write buffer. the max imum number of cycles in the command sequence is 37. 19. acc must be at v hh during the entire operation of this command 20. command sequence resets device for next command after write-to-buffer operation. 21. entry commands are needed to enter a specific mode to enable instructions only available within that mode. 22. write buffer programming can be initiated after unlock bypass entry. command sequence ( note 1 ) cycles bus cycles (notes 1?6) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read ( 7 ) 1 ra rd reset ( 8 ) 1 xxx f0 autoselect ( 9 ) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id ( 10 ) 6 555 aa 2aa 55 555 90 x01 ( 11 )x0e( 10 )x0f( 10 ) indicator bits 4 555 aa 2aa 55 555 90 x03 ( 11 ) program 4 555 aa 2aa 55 555 a0 pa data write to buffer ( 18 ) 6 555 aa 2aa 55 sa 25 pa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset ( 22 ) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend ( 15 ) 1 xxx b0 erase resume ( 15 ) 1 xxx 30 set configuration register ( 16 ) 4 555 aa 2aa 55 555 d0 x00 or x01 cr read configuration register ( 17 ) 4 555 aa 2aa 55 555 c6 x00 or x01 cr unlock bypass mode unlock bypass entry ( 21 ) 3 555 aa 2aa 55 555 20 unlock bypass program ( 12 , 13 )2 xx a0 pa pd unlock bypass reset 2 xx 90 xxx 00 volatile sector protection command set definitions dyb volatile sector protection command set entry 3 555 aa 2aa 55 555 e0 dyb set 2 xx a0 sa 00 dyb clear 2 xx a0 sa 01 dyb status read 1 sa rd(0) volatile sector protection command set exit 2xx 90 xx 00
122 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 22 write operation status the device provides several bits to determine th e status of a program or erase operation: dq1, dq2, dq3, dq5, dq6, and dq7. ta b l e 2 2 . 1 3 and the following subsections describe the function of these bits. dq7 and dq6 each offers a method for determining whether a program or erase operation is complete or in progress. 22.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. note that the data# polling is valid only for the last word being programmed in the write-buffer-page during write buffer programm ing. reading data# polling status on any word other than the last word to be programmed in th e write-buffer-page will return false status information. during the embedded program algorithm, the de vice outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is comple te, the device outputs the datum programmed to dq7. the system must provide the program addr ess to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approxi- mately t psp , then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling pro- duces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asyn- chronously with dq6?dq0 while output enable (o e#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-d00 will appear on successive read cycles. table 22.13 shows the outputs for data# polling on dq7. figure 22.5 shows the data# polling algorithm. figure 25.13 in the ac characteristics section shows the data# polling timing diagram. notes: 1. va = valid adntsbdress for programming. during a sector eras e operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. figure 22.5 data# polling algorithm 22.2 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the device, and is valid after the rising edge of the final we# pulse in the com- mand sequence (prior to the program or erase operation), and during the sector erase time-out.
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 123 data sheet during an embedded program or erase algorith m operation, successive read cycles to any ad- dress cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately t asp (all sectors protected toggle time), then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to dete rmine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog- gling. however, the system must also use dq2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately t psp after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling once the embed- ded program algorithm is complete. see the following for ad ditional information: figure 22.6 , figure 25.14 (toggle bit timing dia- gram), and ta b l e 2 2 . 1 2 . toggle bit i on dq6 requires either oe# or ce# to be deasserted and reasserted to show the change in state. note: the system should recheck th e toggle bit even if dq5 = 1 because the toggle bit may stop toggling as dq5 changes to 1 . see the subsections on dq6 and dq2 for more information. figure 22.6 toggle bit algorithm
124 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 by itself cannot distinguish whether the sector is actively erasing or is erase- suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 2 2 . 1 2 to compare outputs for dq2 and dq6. see figure 22.6 and figure 25.14 for additional information. 22.3 reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would com- pare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the sy stem can read array da ta on dq7?dq0 on the following read cycle. (see figure 22.6 ) however, if after the initial two read cycles, the system determines that the toggle bit is still tog- gling, the system also should note whether the va lue of dq5 is high (see the section on dq5). if it is, the system should then determine again whet her the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went hi gh. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through suc- cessive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. 22.4 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 , indicating that the program or erase cycle was not successfully completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was pre- viously programmed to 0 only an erase operation can change a 0 back to a 1 . under this condition, the device halts the operation, and wh en the timing limit has been exceeded, dq5 pro- duces a 1 . under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previously in the erase-suspend-pro- gram mode). 22.5 dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase time r does not apply to the chip erase command.) if additional sectors are selected for erasure, the en tire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a 0 to a 1 . if
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 125 data sheet the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the syst em should read the status of dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure that th e device has accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algorithm ha s begun; all further commands (ex- cept erase suspend) are ignored until th e erase operation is complete. if dq3 is 00 the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 22.13 shows the status of dq3 relative to the other status bits. 22.6 dq1: write to buffer abort dq1 indicates whether a write to buffer operatio n was aborted. under these conditions dq1 pro- duces a ?1?. the system must issue the write to buffer abort reset command sequence to return the device to reading array data. see the write buffer programming operation section for more details. 3. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer programming operations. note that dq7# during write buffer programming indicates the data-bar for dq7 data for the last loaded write-buffer address location . acc (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +9.5 v 6. minimum dc input voltage on pin acc is -0.5v. during voltage transitions, acc may overshoot table 22.1 maximum negative overshoot waveform figure 22.7 maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v
126 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 23 dc characteristics 23.1 cmos compatible notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. the i cc current listed is typically less than 2-3 ma/mhz, with oe# at v ih . 3. i cc active while embedded erase or embedded program is in progress. 4. device enters automatic sleep mode when addresses are stable for t acc + 20 ns. typical sleep mode current is equal to i cc3 . 5. total current during accelerate d programming is the sum of v acc and v cc currents. 6. u ih = v cc 0.2 v and v il > -.1 v 7. typical test conditions of room temperature and 1.8 v v cc . parameter description test conditions ( note 1 )min ty p ( note 7 ) max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih , burst length = 8 80 mhz 30 66 ma 66 mhz 28 60 54 mhz 27 54 ce# = v il , oe# = v ih , we# = v ih , burst length = 16 80 mhz 32 60 ma 66 mhz 30 54 54 mhz 28 48 ce# = v il , oe# = v ih , we# = v ih , burst length = 32 80 mhz 34 54 ma 66 mhz 32 48 54 mhz 29 42 ce# = v il , oe# = v ih , we# = v ih , burst length = continuous 80 mhz 38 48 ma 66 mhz 35 42 54 mhz 22 36 i cc1 v cc active asynchronous read current ( note 2 ) ce# = v il , oe# = v ih , we# = v ih 10 mhz 27 36 ma 5 mhz 13 18 ma 1 mhz 3 4 ma i cc2 v cc active write current ( note 3 ) ce# = v il , oe# = v ih , acc = v ih v cc <35 <50 ma v acc 20 30 a i cc3 v cc standby current ( note 6 ) ce# = reset# = v cc 0.2 v v cc 20 40 a v acc 10 15 a i cc4 v cc reset current reset# = v il, clk = v il 70 150 a i cc6 v cc sleep current ce# = v il , oe# = v ih 20 40 a i acc accelerated program current ( note 5 ) ce# = v il , oe# = v ih, v acc = 9.5 v v cc <30 <40 ma v acc <15 <20 ma v il input low voltage ?0.5 0.4 v v ih input high voltage v cc ? 0.4 v cc + 0.4 v ol output low voltage i ol = 100 a, v cc = v cc min 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min v cc ? 0.1 v v hh voltage for accelerated program 8.5 9.5 v v lko low v cc lock-out voltage 1.0 1.4 v
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 127 data sheet 24 test conditions figure 24.1 test setup figure 24.2 input waveforms and measurement levels table 24.1 test specifications test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 2.5 ns input pulse levels 0.0?v cc v input timing measurement reference levels v cc /2 v output timing measurement reference levels v cc /2 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) c l device under te s t
128 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 25 ac characteristics 25.1 v cc power-up notes: 1. v cc >= v io - 100mv and v cc ramp rate is > 1v / 100s 2. v cc ramp rate <1v / 100s, a hard ware reset will be required. figure 25.1 v cc power-up diagram 25.2 clk characterization figure 25.2 clk characterization parameter description test setup speed unit t vcs v cc setup time min 1 ms parameter description 80 mhz 66 mhz 54 mhz unit f clk clk frequency max 80 66 54 mhz t clk clk period min 12.5 15.1 18.5 ns t ch clk high time min 3.5 6.1 7.40 ns t cl clk low time t cr clk rise time max 2 3 3 ns t cf clk fall time v cc reset# t vcs t clk t cl t ch t cr t cf clk
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 129 data sheet 25.3 synchronous/burst read notes: 1. addresses are latched on the first rising edge of clk. 2. not 100% tested. parameter description 80 mhz 66 mhz 54 mhz unit jedec standard t iacc latency max 148 ns t bacc burst access time valid clock to output delay max 9.1 11.2 13.5 ns t acs address setup time to clk ( note 1 )min 4 4 5 ns t ach address hold time from clk ( note 1 )min 2 2 3 ns t bdh data hold time from next clock cycle min 4 4 5 ns t cr chip enable to rdy valid max 9.1 11.2 13.5 ns t oe output enable to output valid max 9.1 11.2 13.5 ns t cez chip enable to high z ( note 2 ) max 10 10 10 ns t oez output enable to high z ( note 2 ) max 10 10 10 ns t ces ce# setup time to clk min 4 4 4 ns t rdys rdy setup time to clk min 4 4 5 ns t racc ready access time from clk max 9.1 11.2 13.5 ns t aas address setup time to avd# ( note 1 )min 4 4 5 ns t aah address hold time to avd# ( note 1 )min 2 2 3 ns t cas ce# setup time to avd# min 0 0 0 ns t avc avd# low to clk min 4 4 4 ns t avd avd# pulse min 8 8 8 ns
130 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet notes: 1. figure shows total number of wait states set to ten cycles. the total numb er of wait states can be programmed from three cycles to thirteen cycles. 2. if any burst address occurs at address + 1 , address + 2 , ..., or address + 7 , additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode. 4. in order for the device to operate at 80mhz/66mhz/54mhz, ther e is an additional wait state latency of 2/1/0 accordingly, every 4 clock cycles with the first data being read. figure 25.3 clk synchronous burst mode read da da + 1 da + n oe# data (n) addresses aa avd# rdy (n) clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 10 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z hi-z hi-z 1 2 3 9 10 11 12 t rdys t bacc da + 2 da da + 1 da + n data (n + 1) rdy (n + 1) hi-z hi-z hi-z da + 2 da da + 1 da + n data (n + 2) rdy (n + 2) hi-z hi-z hi-z da + 1 da da da + n data (n + 3) rdy (n + 3) hi-z hi-z hi-z da t cr
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 131 data sheet notes: 1. figure shows total number of wait stat es set to twelve cycles. the total number of wait states can be programmed from three cycles to thirteen cycles. cl ock is set for active rising edge. 2. if any burst address occurs at address + 1 , address + 2 , ..., or address + 7 , additional clock delay cycles are inserted, and are indicated by rdy. the device is in synchronous mode with wrap around. 3. in order for the device to operate at 80mhz/66mhz/54mhz, ther e is an additional wait state latency of 2/1/0 accordingly, every 4 clock cycles with the first data being read. 4. d8?df in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 4th address in range (o-f). figure 25.4 8-word linear burst with wrap around notes: 1. figure shows total number of wait stat es set to twelve cycles. the total number of wait states can be programmed from three cycles to thirteen cycles. cl ock is set for active rising edge. 2. if any burst address occurs at address + 1 , address + 2 , ..., or address + 7 , additional clock delay cycles are inserted, and are indicated by rdy. 3. in order for the device to operate at 80mhz/66mhz/54mhz, ther e is an additional wait state latency of 2/1/0 accordingly, every 4 clock cycles with the first data being read. 4. dc?d13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 4th address in range (c-13). figure 25.5 8-word linear burst without wrap around dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 12 cycles for initial access shown. hi-z t racc 1 2 3 9 10 11 12 t rdys t bacc t cr d8 t racc dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df d13 12 cycles for initial access shown. hi-z t racc 1 2 3 9 10 11 12 t rdys t bacc t cr d10 t racc
132 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet notes: 1. figure assumes eleven wait states for initial access and synchronous read. 2. the set configuration register command sequence has be en written with a18=0; device will output rdy one cycle before valid data. figure 25.6 burst with rdy set one cycle before data 25.4 asynchronous mode read @ vio = 1.8 v notes: 1. asynchronous access time is from the last of ei ther stable addresses or the falling edge of avd#. 2. not 100% tested. parameter description 80 mhz 66 mhz 54 mhz unit jedec standard t ce access time from ce# low max 148 ns t acc asynchronous access time ( note 1 ) max 143 ns t avdp avd# low time min 8 8 10 ns t aavds address setup time to rising edge of avd# min 4 4 5 ns t aavdh address hold time from rising edge of avd# min 2 2 3 ns t oe output enable to output valid max 9.1 11.2 13.5 ns t oeh output enable hold time read min 0 0 0 ns data# polling min 10 10 10 ns t oez output enable to high z ( note 2 ) max 10 10 10 ns t cas ce# setup time to avd# min 0 0 0 ns da+1 da da+2 da+3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 12 wait cycles for initial access shown. hi-z hi-z hi-z 1 2 3 4 10 11 t rdys t bacc t cr
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 133 data sheet 25.5 timing diagrams note: ra = read address, rd = read data. figure 25.7 asynchronous mode read with latched addresses note: ra = read address, rd = read data. figure 25.8 asynchronous mode read 25.6 hardware reset (reset#) note: not 100% tested. parameter description all speeds unit jedec std t rp reset# pulse width min 30 s t rh reset high time before read to read mode min 300 s t rpd reset# low to standby mode min 20 s t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez avd# ra
134 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet figure 25.9 reset timings reset# t rp reset timings ce#, oe# t rh
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 135 data sheet 25.7 erase/program operations notes: 1. not 100% tested. 2. asynchronous read mode allows asynchronous program operation only. synchronous read mode allows both asynchronous and synchronous program operation. 3. in asynchronous program operation timing, addresses are latched on the falling edge of we#. in synchronous program operation timing, addresses are latched on the rising edge of clk. 4. see the erase and programming performance section for more information. does not include the preprogramming time. parameter description 80 mhz 66 mhz 54 mhz unit jedec standard t avav t wc write cycle time ( note 1 )min70ns t avwl t as address setup time (notes 2 , 3 ) synchronous min 5 ns asynchronous 0 0 0 t wlax t ah address hold time (notes 2 , 3 ) synchronous min 223 ns asynchronous 0 0 0 t avdp avd# low time min 8 8 8 ns t dvwh t ds data setup time min 20 20 25 ns t whdx t dh data hold time min 0 0 0 ns t ghwl t ghwl read recovery time before write min 0 0 0 ns t cas ce# setup time to avd# min 0 0 0 ns t wheh t ch ce# hold time min 0 0 0 ns t wlwh t wp write pulse width min 30 ns t whwl t wph write pulse width highs min 20 20 25 ns t sr/w latency between read and write operations min 0 0 0 ns t vid v acc rise and fall time min 500 ns t vids v acc setup time (during acce lerated programming) min 1 s t vcs v cc setup time min 50 s t elwl t cs ce# setup time to we# min 5 ns t avsw avd# setup time to we# min 5 ns t avhw avd# hold time to we# min 2 2 3 ns t avsc avd# setup time to clk min 5 ns t avhc avd# hold time to clk min 2 2 3 ns t csw clock setup time to we# min 5 ns t wep noise pulse margin on we# max 3 ns t sea sector erase accept time-out max 50 s t esl erase suspend latency max 20 s t psl program suspend latency max 20 s t asp toggle time during sector protection typ 100 s t psp toggle time during programming within a protected sector typ 1 s
136 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. amax?a14 are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is independent of th e set device read mode bit in the configuration register. figure 25.10 asynchronous program operation timings: we# latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t as t avsw t avhw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs t cas
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 137 data sheet notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. amax9?a14 are don?t care during command sequence unlock cycles. 4. addresses are latched on the rising edge of clk. 5. either ce# or avd# is required to go from low to high in be tween programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 25.11 synchronous program operation timings: clk latched addresses note: use setup and hold times from conventional program operation. figure 25.12 accelerated unlock bypass programming timing oe# ce# data addresses avd# we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw t avsc ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id v il or v ih t vid t vids
138 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is completedata# polling will output true data. figure 25.13 data# polling timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete, . figure 25.14 toggle bit timings (during embedded algorithm) we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 139 data sheet notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete, . 3. rdy is active with data (d8 = 0 in the configuration register). when d8 = 1 in the configuration register, rdy is active one clock cycle before data. figure 25.15 synchronous data polling ti mings/toggle bit timings note: dq2 toggles only when read at an address within an er ase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 25.16 dq2 vs. dq6 ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
140 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet notes: 1. rdy active with data (d8 = 0 in the configuration register). 2. rdy active one clock cycle before data (d8 = 1 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. there will be an additional 4/8 wait state latency for 54/80 mhz respectively. figure 25.17 latency with boundary crossing wait state configuration register setup note: figure assumes address d0 is not at an address boundary. figure 25.18 example of wait states insertion cr1.0, cr0.13, cr0.12, cr0.11= 1101 ? 13 total cr1.0, cr0.13, cr0.12, cr0.11= 1100 ? 12 total cr1.0, cr0.13, cr0.12, cr0.11= 1011 ? 11 total cr1.0, cr0.13, cr0.12, cr0.11= 1010 ? 10 total cr1.0, cr0.13, cr0.12, cr0.11= 1001 ? 9 total cr1.0, cr0.13, cr0.12, cr0.11= 1000 ? 8 total cr1.0, cr0.13, cr0.12, cr0.11= 0101 ? 7 total cr1.0, cr0.13, cr0.12, cr0.11= 0100 ? 6 total cr1.0, cr0.13, cr0.12, cr0.11= 0011 ? 5 total cr1.0, cr0.13, cr0.12, cr0.11= 0010 ? 4 total cr1.0, cr0.13, cr0.12, cr0.11= 0001 ? 3 total clk address (hex) c508 c509 c510 c511 c511 c512 c513 c514 c515 d508 d509 d510 d511 d512 d513 d514 (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 512 words, beginning at address 0001ffh: (0002ffh, 0003ffh, etc.) address 000000h is also a boundary crossing. 1fc 1fd 1fe 1ff 1ff 200 201 202 203 latency rdy(2) latency t racc t racc t racc t racc data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following avd# falling edge rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45 8 9 10 11 12 13 14
february 17, 2005 s75ws-n-00_00_a0 s75ws256nxx based mcps 141 data sheet note: breakpoints in waveforms indicate that system may alternat ely read the status of the program or erase operation in the device. the system should read status twice to ensure valid information. figure 25.19 back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
142 s75ws256nxx based mcps s75ws-n-00_00_a0 february 17, 2005 data sheet 26 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 1.8 v v cc , 100,000 cycles typical. additionally, programming typically assumes a checkerboard pattern. 2. under worst case conditions of 90c, v cc = 1.65 v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see the command definitions table for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 100,000 cycles. parameter ty p ( note 1 ) max ( note 2 ) unit comments sector erase time 256 kword v cc 220 s excludes 00h programming prior to erasure ( note 4 ) acc 1 10 chip erase time v cc 308 616 s acc 262 524 word programming time v cc <40 <400 s excludes system level overhead ( note 5 ) acc <24 <240 effective word programming time utilizing program write buffer v cc <9.4 <94 s acc <6 <60 total 32-word bufferprogramming time v cc <300 <3000 s acc <192 <1920 chip programming time ( note 3 ) v cc <314.6 <629.2 s excludes system level overhead ( note 5 ) acc <201.4 <402.6
publication number s75ws-n-00 revision a amendment 0 issue date february 17, 2005 cellularram 128/64/32 megabit burst cellularram features ? single device supports asynchronous, page, and burst operations ? vcc voltages ? 1.70v?1.95v v cc ? random access time: 70ns ? burst mode write access ? continuous burst ? burst mode read access ? 4, 8, or 16 words, or continuous burst ? page mode read access ? sixteen-word page size ? interpage read access: 70ns ? intrapage read access: 20ns ? low-power consumption ? asynchronous read < 25ma ? intrapage read < 15ma ? initial access, burst read < 35ma ? continuous burst read < 11ma ? standby: 180a ? deep power-down < 10a ? low-power features ? temperature compensated refresh (tcr) on-chip sensor control ? partial array refresh (par) ? deep power-down (dpd) mode general description cellularram? products are high-s peed, cmos dynamic random acce ss memories developed for low- power, portable applications. these devices include an industry standard burst mode flash interface that dramatically increases read/write bandwidth compar ed with other low-power sram or pseudo sram offerings. to operate seamlessly on a burst flash bus, cellular ram products incorporate a transparent self-refresh mechanism. the hidden refresh requires no addition al support from the system memory controller and has no significant impact on device read/write performance. two user-accessible control registers define device operation. the bus configuration register (bcr) de - fines how the cellularram device interacts with the system memory bus and is nearly identical to its counterpart on burst mode flash devices. the refresh configuration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. special attention has been focused on standby current consumption during self refresh. cellularram prod - ucts include three mechanisms to minimize standby current. partial array refresh (par) enables the system to limit refresh to only that part of the dram array that contains essential data. temperature com - pensated refresh (tcr) adjusts the refresh rate to match the device temperature?the refresh rate decreases at lower temperatures to minimize current consumption during standby. deep power-down (dpd) enables the system to halt the refresh operatio n altogether when no vital information is stored in the device. the system-configurable refresh mechanisms are accessed through the rcr.
144 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 27 functional block diagram note: functional block diagrams illustrate si mplified device operation. see truth table, ball descriptions, and timing di- agrams for detailed information. figure 27.1 functional block diagram 128m: a[22:0] 64m: a[21:0] 32m: a[20:0] input/ output mux and buffers control logic dram memory array ce# we# oe# clk adv# cre wait lb# ub# dq[7:0] dq[15:8] address decode logic refresh configuration register (rcr) bus configuration register (bcr)
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 145 advance information note: the clk and adv# inputs can be tied to v ss if the device is always operating in asynchronous or page mode. wait will be asserted but should be ignored during asynchronous and page mode operations. table 27.1 signal descriptions symbol type description 128m: a[22:0] 64m: a[21:0] 32m: a[20:0] input address inputs: inputs for a ddresses during read and write operations. addresses are internally latched during read and write cycles. the address lines are also used to define the value to be loaded into the bcr or the rcr. clk input clock: synchronizes the memory to the system operating frequency during synchronous operations. when configured for synchronous operation, the address is latched on the first rising clk edge when adv# is active. clk is static (high or low) during asynchronous access read and write operations and during page read access operations. adv# input address valid: indicates that a valid address is present on the address inputs. addresses can be latched on the rising edge of adv# du ring asynchronous read and write operations. adv# can be held low during asynchronous read and write operations. cre input configuration register enable: when cre is high, write operations load the rcr or bcr. ce# input chip enable: activates the device when low. wh en ce# is high, the device is disabled and goes into standby or deep power-down mode. oe# input output enable: enables the output buffers when low. when oe# is high, the output buffers are disabled. we# input write enable: determin es if a given cycle is a write cycle. if we# is low, the cycle is a write to either a configuration regi ster or to the memory array. lb# input lower byte enable. dq[7:0] ub# input upper byte enable. dq[15:8] dq[15:0] input/ output data inputs/outputs. wait output wait: provides data-valid feedback during burst read and write operations. the signal is gated by ce#. wait is used to arbitrat e collisions between re fresh and read/write operations. wait is asserted when a burst crosse s a row boundary. wait is also used to mask the delay associated with opening a new internal page. wait is asserted and should be ignored during asynchronous an d page mode operations. wait is high-z when ce# is high. v cc supply device power supply: (1.7v?1.95v) power supply for device core operation. v cc q supply i/o power supply: (1.7v?1.95v) power supply for input/output buffers. v ss supply v ss must be connected to ground. v ss qsupplyv ss q must be connected to ground.
146 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. clk may be high or low, but must be static during synchronous read, synchronous write, burst suspend, and dpd modes; and to a chieve standby power during standby and active modes. 2. the wait polarity is configured through the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are affected. when only lb # is in select mode, dq[7:0] are affected. when only ub# is in the select mode , dq[15:8] are affected. 4. the device will consume active power in this mode whenever addresses are changed. 5. when the device is in standby mode, address inputs and data in puts/outputs are internally isolated from any external influenc e. 6. v in = v cc q or 0v; all device balls must be static (unswitched) to achieve standby current. 7. dpd is maintained unt il rcr is reconfigured. table 27.2 bus operations?asynchronous mode mode power clk ( note 1 ) adv# ce# oe# we# cre lb#/ ub# wait ( note 2 ) dq[15:0] ( note 3 )notes read active x l l l h l l low-z data-out 4 write active x llxllllow-zdata-in 4 standby standby x x h x x l x high-z high-z 5 , 6 no operation idle x x l x x l x low-z x 4 , 6 configuration register active x llhlhxlow-zhigh-z dpd deep power-down x x h x x x x high-z high-z 7
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 147 advance information notes: 1. clk may be high or low, but must be static during asynchronous read, synchronous write, burst suspend, and dpd modes; and to achieve standby power during standby and active modes. 2. the wait polarity is configured through the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are affected. when only lb # is in select mode, dq[7:0] are affected. when only ub# is in the select mode , dq[15:8] are affected. 4. the device will consume active power in this mode whenever addresses are changed. 5. when the device is in standby mode, address inputs and data in puts/outputs are internally isolated from any external influenc e. 6. v in = v cc q or 0v; all device balls must be static (unswitched) to achieve standby current. 7. dpd is maintained unt il rcr is reconfigured. 8. burst mode operation is initialized through the bus configuration register (bcr[15]). table 27.3 bus operations?burst mode mode power clk ( note 1 ) adv# ce# oe# we# cre lb#/ ub# wait ( note 2 ) dq[15:0] ( note 3 )notes async read active x l l l h l l low-z data-out 4 async write active x llxllllow-z data-in 4 standby standby x x h x x l x high-z high-z 5 , 6 no operation idle x x l x x l x low-z x 4 , 6 initial burst read active l l x h l l low-z data-out 4 , 8 initial burst write active l l h l l x low-z data-in 4 , 8 burst continue active h l x x l x low-z data-in or data-out 4 , 8 burst suspend active x x l h x l x low-z high-z 4 , 8 configuration register active l l h l h x low-z high-z 8 dpd deep power-down x x h x x x x high-z high-z 7
148 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 28 functional description the cellularram bus interface supports both asynchronous and burst mode transfers. page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. 28.1 power-up initialization cellularram products include an on -chip voltage sensor used to launch the power-up initialization process. initialization will configure the bcr and the rcr with their default settings (see table 31.1 and ta b l e 3 1 . 5 ). v cc and v ccq must be applied simultaneously. when they reach a sta- ble level at or above 1.7v, the device will require 150 s to complete its self-initialization process. during the initialization period, ce# should remain high. when initialization is complete, the de- vice is ready for normal operation. figure 28.2 power-up initialization timing v cc v ccq t pu > 150 s device initialization device ready for normal operation v cc = 1.7 v
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 149 advance information 29 bus operating modes cellularram products incorporate a burst mode in terface found on flash products targeting low- power, wireless applications. this bus interf ace supports asynchronous , page mode, and burst mode read and write transfers. the specific interface supported is defined by the value loaded into the bcr. page mode is controlled by the refresh configuration register (rcr[7]). 29.1 asynchronous mode cellularram products power up in the asynchronous operating mode. this mo de uses the industry standard sram control bus (ce#, oe#, we#, lb#/ ub#). read operations ( figure 29.1 ) are ini- tiated by bringing ce#, oe#, and lb#/ub# low wh ile keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations ( figure 29.2 ) occur when ce#, we#, and lb#/ ub# are driven low. during asynchronous write operations, the oe# level is a don't care , and we# will override oe#. the data to be written is latched on the rising edge of ce#, we#, or lb#/ub# (whichever occu rs first). asynchronous operations (page mode disabled) can either use the adv input to latch the address, or adv can be driven low during the entire read/write operation. during asynchronous operation, the clk input must be held static (high or low, no transitions). wait will be driven while the device is enabled and its state should be ignored. note: adv must remain low fo r page mode operation. figure 29.1 read operation (adv# low) data valid address valid t rc = read cycle time ce# oe# we# address data lb#/ub# don't care
150 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 29.2 page mode read operation page mode is a performance-enhancing extension to the legacy asynchronous read operation. in page mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changi ng the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. addresses a[4] and higher must remain fixed during the entire page mode access. figure 29.3 shows the timing for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than rand om addresses. write operations do not include comparable page mode functionality. during asynchronous page mode operation, the cl k input must be held low. ce# must be driven high upon completion of a page mode access. wait will be driven while the device is enabled and its state should be ignored. page mode is enable d by setting rcr[7] to hi gh. write operations do not include comparable page mode functionality. adv must be driven low during all page mode read accesses. figure 29.2 write operation (adv# low) data valid address valid t wc = write cycle time ce# oe# we# address data lb#/ub# don't care
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 151 advance information 29.3 burst mode operation burst mode operations enable high-speed sync hronous read and write operations. burst opera- tions consist of a multi-clock sequence that must be performed in an ordered fashion. after ce# goes low, the address to access is latched on the rising edge of the next clock that adv# is low. during this first clock rising edge, we# indicate s whether the operation is going to be a read (we# = high, figure 29.4 ) or write (we# = low, figure 29.5 ). the size of a burst can be specified in the bcr either as a fixed length or continuous. fixed-length bursts consist of four, eight, or sixteen words. continuous bursts have the ability to start at a specified address and burst through the entire memory. the latency count stored in the bcr defines the number of clock cycles that elapse before the initial data value is transferred between the processor and cellularram device. the wait output asserts as soon as a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of) the memory. wait will again be asserted if the burst crosses a row boundary. once the cellularram device has restored the previous row's data and accessed the next row, wait will be deasserted and the burst can continue (see figure 34.9 ). to access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. bursts are suspended by stopping cl k. clk can be stopped high or low. if another device will use the data bus while the burst is suspended, oe# should be taken high to disable the cellularram outputs; otherwise, oe# can remain low. note that the wait output will continue to be active, and as a result no other devices should directly share the wait connection to the controller. to continue the burst sequence, oe# is taken low, then clk is restarted after valid data is available on the bus. see how extended timings impact cellularram? operation for restrictions on the maximum ce# low time during burst operations. if a burst susp ension will cause ce# to remain low for longer than t cem , ce# should be taken high and the burs t restarted with a new ce# low/adv# low cycle. figure 29.3 page mode read operation (adv# low) ce# oe# we# address data lb#/ub# don't care add[1] add[2] add[3] t aa d[0] t apa d[1] t apa d[2] t apa d[3] add[0]
152 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information note: non-default bcr settings: variable late ncy; latency code two (three clocks); wait active low; wait asserted dur- ing delay. figure 29.4 burst mode read (4-word burst) note: non-default bcr settings: variable late ncy; latency code two (three clocks); wait active low; wait asserted dur- ing delay. figure 29.5 burst mode write (4-word burst) don't care undefined legend: latency code 2 (3 clocks), variable d[0] d[1] d[2] d[3] read burst identified (we# = high) clk a[22:0] adv# ce# oe# we# wait dq[15:0] lb#/ub# address valid address valid latency code 2 (3 clocks), variable write burst identified (we# = low) clk a[22:0] adv# ce# oe# we# wait dq[15:0] lb#/ub# d[0] d[1] d[2] d[3] don't care legend:
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 153 advance information 29.4 mixed-mode operation the device can support a combination of synchr onous read and asynchronous write operations when the bcr is configured for synchronous op eration. the asynchrono us write operation re- quires that the clock (clk) remain static (high or low) during the entire sequence. the adv# signal can be used to latch the target address, or it can remain low during the entire write oper- ation. ce# can remain low when transitioning be tween mixed-mode operations with fixed latency enabled. note that the t cka period is the same as a read or write cycle. this time is required to ensure adequate refresh. mixed-mode operation facilitates a seamless interface to legacy burst mode flash memory controllers. see figure 34.18 , asynchronous write followed by burst read (timing diagram). 29.5 wait operation the wait output on a cellularram device is typically connected to a shared, system-level wait sig- nal ( figure 29.6 ). the shared wait signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. once a read or write operation has been initiated, wait goes active to indicate that the cellular- ram device requires additional time before data can be transferred. for read operations, wait will remain active until valid data is output from the device. for write operations, wait will indicate to the memory controller when data will be accepted into the cellularram device. when wait tran- sitions to an inactive state, the data burst will progress on successive clock edges. ce# must remain asserted during wait cycles (wait asserted and wait configuration bcr[8] = 1). bringing ce# high during wait cycles may cause data corruption. (note that for bcr[8] = 0, the actual wait cycles end one cycle after wait de-asserts, and for row boundary crossings, start one cycle after the wait signal asserts.) when using variable initial access latency (bcr[14] = 0), the wait output performs an arbitration role for read or write operations launched while an on-chip refresh is in progress. if a collision occurs, the wait pin is asserted for additional clock cycles until the refresh has completed ( figure 29.7 and figure 29.8 ). when the refresh operation has completed, the read or write op- eration will continue normally. wait is also asserted when a continuous read or write burst crosses the boundary between 128- word rows. the wait assertion allows time for the new row to be accessed, and permits any pend- ing refresh operations to be performed. wait will be asserted but should be ignored during asynchronous read and write, and page read operations. 29.6 lb#/ub# operation the lb# enable and ub# enable signals support byte-wide data transfers. during read opera- tions, the enabled byte(s) are driven onto the dq s. the dqs associated with a disabled byte are put into a high-z state during a read operation. during write operations, any disabled bytes will figure 29.6 wired or wait configuration cellularram external pull-up/ pull-down resistor processor ready other device wait other device wait wait
154 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information not be transferred to the ram array and the intern al value will remain unchanged. during an asyn- chronous write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (high) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, it remains in an active mode as long as ce# remains low. note: non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. figure 29.7 refresh collision during read operation additional wait states inserted to allow refresh completion. clk a[22:0] adv# ce# oe# we# wait dq[15:0] lb#/ub# don't care undefined legend: v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il high-z v oh v ol d[0] d[1] d[2] d[3] v oh v ol address valid
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 155 advance information note: non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. figure 29.8 refresh collision during write operation address valid additional wait states inserted to allow refresh completion. clk a[22:0] adv# ce# oe# we# wait dq[15:0] lb#/ub# don't care legend: v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il high-z v oh v ol d[1] d[2] d[3] v oh v ol d[0]
156 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 30 low-power operation 30.1 standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation. standby op eration occurs when ce# is high. the device will enter a reduced power state upon completion of a read or write operation, or when the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. 30.2 temperature compensated refresh temperature compensated refresh (tcr) is used to adjust the refresh rate depending on the de- vice operating temperature. dram technology requ ires increasingly frequent refresh operation to maintain data integrity as temperatures increase. more frequent refresh is required due to in- creased leakage of the dram ca pacitive storage elements as temperatures rise. a decreased refresh rate at lower temperatures will facilitate a savings in standby current. tcr allows for adequate refresh at four different temperature thresholds (+15 c, +45 c, +70 c, and +85 c). the setting selected must be for a temperature higher than the case temperature of the cellularram device. for example, if the case temperature is 50 c, the system can minimize self refresh current consumption by selecting the +7 0c setting. the +15 c and +45 c settings would result in inadequate refres hing and cause data corruption. 30.3 partial array refresh partial array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quarter array, three-quarter array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map ( ta b l e 3 1 . 6 ). read and write operations to address ranges receiving refresh will not be affected. data stored in addresses not receiving refresh will become corrupted. when re-enabling additional po rtions of the array, the new portions are avail- able immediately upon writing to the rcr. 30.4 deep power-down operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellularram device. any stored data will be- come corrupted when dpd is enabled. when refresh activity has been re-enabled by rewriting the rcr, the cellularram device will require 150s to perform an initialization procedure before nor- mal operations can resume. during this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. dpd cannot be enabled or disabled by writing to the rcr using the software access sequence; the rcr should be accessed using cre instead.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 157 advance information 31 configuration registers two user-accessible configuration registers define the device operation. the bus configuration register (bcr) defines how the cellularram interacts with the system memory bus and is nearly identical to its counterpart on burst mode flash devices. the refresh configuration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up, an d can be updated any time the devices are op- erating in a standby state. 31.1 access using cre the configuration registers can be written to usin g either a synchronous or an asynchronous op- eration when the configuration register enable (cre) input is high (see figure 31.1 and figure 31.2 ). when cre is low, a read or write operation will access the memory array. the reg- ister values are written via address pins a[21:0]. in an asynchronous write, the values are latched into the configuration register on the rising edge of adv#, ce#, or we#, whichever oc- curs first; lb# and ub# are don?t care . the bcr is accessed when a[19] is high; the rcr is accessed when a[19] is low. for reads, address inputs other than a[19] are don?t care , and reg- ister bits 15:0 are output on dq[15:0].
158 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information note: a[19] = low to load rcr; a[19] = high to load bcr. figure 31.1 configuration register write, asynchronous mode followed by read select control register opcode address t avs t avh address t avs t avh t vph t vp t cbph initiate control register access t cw t wp write address bus value to control register data valid don't care legend: a[22:0] (except a19) a19 (note) cre adv# ce# oe# we# lb#/ub# dq[15:0]
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 159 advance information figure 31.2 configuration register write, synchronous mode followed by read0 notes: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. 2. a[19] = low to load rcr; a[19] = high to load bcr. 3. ce# must remain low to complete a burst-of-one write. wait must be monitored? additional wait cycles caused by refresh collisi ons require a corresponding number of additional ce# low cycles. latch control register value address address t hd opcode t sp latch control register address t sp t hd t sp t hd t csp t cbph (note 3) high-z high-z t cew data valid clk a[22:0] (except a19) a19 (note 2) cre adv# ce# oe# we# lb#/ub# wait dq[15:0] don't care legend: t sp t hd
160 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 31.2 bus configuration register the bcr defines how the cellularram device interacts with the system memory bus. page mode operation is enabled by a bit contained in the rcr. ta b l e 3 1 . 1 below describes the control bits in the bcr. at powerup, the bcr is set to 9d4fh. the bcr is accessed using cre and a[19] high. table 31.1 bus configuration register definition note: burst wrap and length apply to read operations only. a13 11 0 latency counter initial latency 321 wait polarity 4 5 6 7 8 output impedance burst wrap (bw) (note) 14 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 output impedance full drive (default) 1/2 drive 1/4 drive reserved bcr[5] 0 0 1 1 bcr[4] 0 1 0 1 15 burst length (bl) (note) reserved reserved 9 10 operating mode 0 1 wait polarity active low active high (default) bcr[10] reserved 22?20 a14 a15 a[18:16] 19 18?16 register select reserved a19 a[22:20] reserved must be set to "0" must be set to "0" all must be set to "0" 0 1 operating mode synchronous burst access mode asynchronous access mode (default) bcr[15] 0 1 register select select rcr select bcr bcr[19] burst wrap (note) burst wraps within the burst length burst no wrap (default) bcr[3] 0 1 must be set to "0" setting is ignored wait configuration (wc) 12 13 bcr[12] bcr[11] latency counter bcr[13] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 code 0?reserved code 1?reserved code 2 code 3 (default) code 4 code 5 code 6 code 7?reserved 0 1 wait configuration asserted during delay asserted one data cycle before delay (default) bcr[8] bcr[1] bcr[0] burst length (note) bcr[2] 0 0 0 1 0 1 1 1 1 0 1 1 4 words 8 words 16 words continuous burst (default) reserved must be set to "0" others
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 161 advance information 31.2.1 burst length (bcr[2:0]): default = continuous burst burst lengths define the number of words the device outputs during burst read operations. the device supports a burst length of 4, 8, or 16 word s. the device can also be set in continuous burst mode where data is accessed sequentially withou t regard to address boundaries. enabling burst no-wrap with bcr[3] = 1 overrides the burst-length setting. 31.2.2 burst wrap (bcr[3]): default = no wrap the burst-wrap option determines if a 4-, 8-, or 16-word read burst wraps within the burst length or steps through sequential addresses. if the wrap option is not enabled, the device accesses data from sequential addresses without regard to bu rst boundaries. when continuous burst operation is selected, the internal address wraps to 000000h if the burst goes past the last address. en- abling burst nowrap (bcr[3] = 1) ov errides the burst-length setting. 31.2.3 output impedance (bcr[5:4]) : default = outputs use full drive strength the output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. the reduced-strength options are intended for stacked chip (flash + cellularram) environments when ther e is a dedicated memory bus. the reduced-drive- table 31.2 sequence and burst length burst wrap starting address 4-word burst length 8-word burst length 16-wor d burst length continuous burst bcr[3] wrap (decimal) linear linear linear linear 0yes 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-? 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-? 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-? 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-? 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-? 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-? 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12-? 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-? ? ?? 14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-? 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21? 1no 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-? 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-? 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-5-6-7-8-? 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-6-7-8-9-? 4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-? 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-?-15-16-17-18-19-20 5-6-7-8-9-10-11? 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-?-16-17-18-19-20-21 6-7-8-9-10-11-12? 7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-?-17-18-19-20-21-22 7-8-9-10-11-12-13? ? ?? 14 14-15-16-17-18-19-?-23-24-25-26-27-28-29 14-15-16-17-18-19-20-? 15 5-16-17-18-19-20-?-24-25-26-27-28-29-30 15-16-17-18-19-20-21-?
162 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information strength option minimizes the noise generated on the data bus during read operations. normal output drive strength should be selected when using a discrete cellularram device in a more heavily loaded data bus environment. outputs are co nfigured at full drive strength during testing. 31.2.4 wait configuration (bcr[8]) : default = wait transitions one clock before data valid/invalid the wait configuration bit is used to determine when wait transitions between the asserted and the de-asserted state with respect to valid data pr esented on the data bus. the memory controller will use the wait signal to coordinate data transfer during synchronous read and write operations. when bcr[8] = 0, data will be valid or invalid on the clock edge immediately after wait transitions to the de-asserted or asserted state, respectively ( figure 31.3 and figure 31.5 ). when a8 = 1, the wait signal transitions one clock period prior to the data bus going valid or invalid ( figure 31.4 ). 31.2.5 wait polarity (bcr[10]): default = wait active high the wait polarity bit indicates whether an asserted wait output should be high or low. this bit will determine whether the wait signal requires a pull-up or pull-down resistor to maintain the de- asserted state. table 31.3 output impedance bcr[5] bcr[4] drive strength 00 full 01 1/2 10 1/4 11reserved note: data valid/invalid immediately afte r wait transitions (bcr[8] = 0). see figure 31.5 . figure 31.3 wait configuration (bcr[8] = 0) note: valid/invalid data delayed for one clock after wait transitions (bcr[8] = 1). see figure 31.5 . figure 31.4 wait configuration (bcr[8] = 1) data[0] data[1] high-z clk wait dq[15:0] data immediately valid (or invalid) data[0] high-z clk wait dq[15:0] data valid (or invalid) after one clock delay
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 163 advance information 31.2.6 latency counter (bcr[13:11]) : default = three-clock latency the latency counter bits determine how many cloc ks occur between the beginning of a read or write operation and the first data value transferred. latency codes from two (three clocks) to six (seven clocks) are allowed (see ta b l e 3 1 . 4 and figure 31.6 below). note: latency is the number of clock cycles from the initiation of a burst operation until data appears. data is trans- ferred on the next clock cycle. note: non-default bcr setting: wait active low. figure 31.5 wait configuration during burst operation table 31.4 variable latency configuration codes bcr[13:11] latency configuration code latency (note) max input clk frequency (mhz) normal refresh collision 70 ns/80 mhz 85 ns/66 mhz 010 2 (3 clocks) 2 4 75 (13.0 ns) 44 (22.7 ns) 011 3 (4 clocks)?default 3 6 80 (12.5 ns) 66 (15.2 ns) 100 4 (5 clocks) 4 8 figure 31.6 latency counter (variable initial latency, no refresh collision) d[0] d[1] d[2] d[3] d[4] clk wait wait dq[15:0] bcr[8] = 0 data valid in current cycle bcr[8] = 1 data valid in next cycle don't care legend: code 2 valid output valid output valid output valid output valid address valid output code 3 (default) valid output valid output valid output valid output code 4 valid output valid output valid output v ih v il v ih v il v ih v il v oh v ol v oh v ol v oh v ol clk a[21:0] adv# a/dq[15:0] a/dq[15:0] a/dq[15:0] don't care undefined legend:
164 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 31.2.7 operating mode (bcr[15]): default = asynchronous operation the operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. 31.3 refresh configuration register the refresh configuration register (rcr) defines how the cellular ram device performs its trans- parent self refresh. altering the refresh parameters can dramatically reduce current consumption during standby mode. page mode control is also embedded into the rcr. ta b l e 3 1 . 5 below de- scribes the control bits used in the rcr. at power-up, the rcr is set to 0070h. the rcr is accessed using cre and a[19] low. 31.3.1 partial array refresh (rcr[2 :0]): default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quarter array, three- quarters array, or none of the array. the mapping of these partitions can start at either the be- ginning or the end of the address map (see table 31.6 through ta b l e 3 1 . 8 ). table 31.5 refresh configuration register mapping table 31.6 128mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?7fffffh 8 meg x 16 128mb 0 0 1 one-half of die 000000h?3fffffh 4 meg x 16 64mb 0 1 0 one-quarter of die 000000h?1fffffh 2 meg x 16 32mb 0 1 1 one-eighth of die 000000h?0fffffh 1 meg x 16 16mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 400000h?7fffffh 4 meg x 16 64mb par a4 a3 a2 a1 a0 read configuration register address bus a5 a6 all must be set to "0" 0 1 deep power-down dpd enable dpd disable (default) rcr[4] a[18:8] register select reserved reserved reserved tcr a[22:20] a19 0 1 register select select rcr select bcr rcr[19] all must be set to "0" rcr[1] rcr[0] refresh coverage rcr[2] 0 0 full array (default) 0 0 1 bottom 1/2 array 0 1 0 bottom 1/4 array 0 1 1 bottom 1/8 array 0 01 1 top 1/2 array 10 1 top 1/4 array dpd must be set to "0" a7 page 0 1 page mode enable/disable page mode disabled (default) page mode enable rcr[7] 4 51 2 30 6 18?8 19 22?20 7 1 none of array 00 1 top 3/4 array 11 rcr[6] rcr[5] maximum case temp +85oc (default) 11 00 01 10 +70oc +45oc +15oc
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 165 advance information 31.3.2 deep power-down (rcr [4]): default = dpd disabled the deep power-down bit enables and disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellular- ram device will require 150s to perform an initialization procedure before normal operations can resume. deep power-down is enabled when rcr[4] = 0, and remains enabled until rcr[4] is set to 1 . 31.3.3 temperature compensated refresh (rcr[6:5]): default = +85oc operation the tcr bits allow for adequate refresh at four different temperature thresholds (+15oc, +45oc, +70oc, and +85oc). the setting selected must be for a temperature higher than the case tem- perature of the cellurlarram device. if the case temperature is +50oc, the system can minimize self refresh current consumption by selecting the +70oc setting. the +15oc and +45oc settings would result in inadequate refres hing and cause data corruption. 1 1 0 one-quarter of die 600000h?7fffffh 2 meg x 16 32mb 1 1 1 one-eighth of die 700000h?7fffffh 1 meg x 16 16mb table 31.7 64mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?3fffffh 4 meg x 16 64mb 0 0 1 one-half of die 000000h?2fffffh 3 meg x 16 48mb 0 1 0 one-quarter of die 000000h?1fffffh 2 meg x 16 32mb 0 1 1 one-eighth of die 000000h?0fffffh 1 meg x 16 16mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 100000h?3fffffh 3 meg x 16 48mb 1 1 0 one-quarter of die 200000h?3fffffh 2 meg x 16 32mb 1 1 1 one-eighth of die 300000h?3fffffh 1 meg x 16 16mb table 31.8 32mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?1fffffh 2 meg x 16 32mb 0 0 1 one-half of die 000000h?17ffffh 1.5 meg x 16 24mb 0 1 0 one-quarter of die 000000h?0fffffh 1 meg x 16 16mb 0 1 1 one-eighth of die 000000h?07ffffh 512k x 16 8mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 080000h?1fffffh 1.5 meg x 16 24mb 1 1 0 one-quarter of die 100000h?1fffffh 1 meg x 16 16mb 1 1 1 one-eighth of die 180000h?1fffffh 512k x 16 8mb table 31.6 128mb address patterns for par (rcr[4] = 1) (continued) rcr[2] rcr[1] rcr[0] active section address space size density
166 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 31.3.4 page mode operation (rcr[7]): default = disabled the page mode operation bit determines whether page mode is enabled for asynchronous read operations. in the power-up defaul t state, page mode is disabled.
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 167 advance information 32 absolute maximum ratings voltage to any ball except v cc , v cc q . . . . . . . . . . . . . . . . . . . . . . . . . . . . relative to v ss -0.50v to (4.0v or v cc q + 0.3v, whichever is less) voltage on v cc supply relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to +2.45v voltage on v cc q supply relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to +2.45v storage temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oc to +150oc operating temperature (case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . wireless-25oc to +85oc note: *stresses greater than those listed may cause pe rmanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
168 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 33 dc characteristics notes: 1. wireless temperature (-25oc < tc < +85oc); industrial temperature (-40oc < tc < +85oc). 2. input signals may overshoot to v cc q + 1.0v for periods less than 2ns during transitions. 3. input signals may undershoot to v ss - 1.0v for periods less th an 2ns during transitions. 4. bcr[5:4] = 00b. 5. this parameter is specified with the outp uts disabled to avoid external loading effects. the user must add the current requir ed to drive output capacitance expected in the actual system. 6. isb (max) values measured with par set to full array and tcr se t to +85c. to achieve low standby current, all inputs must be driven to either v cc q or v ss . table 33.1 electrical characteristics and operating conditions description conditions symbol min max units notes supply voltage v cc 1.70 1.95 v i/o supply voltage v cc q w: 1.8v 1.70 1.95 v j: 1.5v 1.35 1.65 v input high voltage v ih v cc q - 0.4 v cc q + 0.2 v 2 input low voltage v il -0.20 0.4 v 3 output high voltage i oh = -0.2ma v oh 0.80 v cc qv 4 output low voltage i ol = +0.2ma v ol 0.20 v cc qv 4 input leakage current v in = 0 to v cc qi li 1a output leakage current oe# = v ih or chip disabled i lo 1a operating current asynchronous random read v in = v cc q or 0v chip enabled, iout = 0 i cc 1 -70 25 ma 5 -85 20 asynchronous page read -70 15 -85 12 initial access, burst read v in = v cc q or 0v chip enabled, iout = 0 i cc 1 80 mhz 35 ma 5 66 mhz 30 continuous burst read 80 mhz 18 66 mhz 15 write operating current v in = v cc q or 0v chip enabled i cc 2 -70 25 ma -85 20 standby current v in = v cc q or 0v ce# = v cc q i sb 128 m 180 a 6 64 m 120 32 m 110
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 169 advance information note: i par (max) values measured with tcr set to 85c. ta b l e 3 3 . 3 partial array refresh specifications and conditions note:i par (max) values measured with tcr set to 85c. table 33.2 temperature compensated refresh specifications and conditions description conditions symbol density max case te m p e r a t u r e standard power (no desig.) units temperature compensated refresh standby current v in = v cc q or 0v, ce# = v cc q i tcr 64 mb +85 c 120 a +70 c 105 +45 c85 +15 c70 32 mb +85 c 110 +70 c95 +45 c80 +15 c70 description conditions symbol density array partition standard power (no desig.) units partially array refresh standby current v in = v cc q or 0v, ce# = v cc q i par 64 mb full 120 a 1/2 115 1/4 110 1/8 105 0 70 32 mb full 110 1/2 105 1/4 100 1/8 95 0 70 128 mb full 180 0 50 table 33.4 deep power-down specifications description conditions symbol typ units deep power-down v in = v cc q or 0v; +25c; v cc = 1.8v i zz 10 a
170 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 34 ac characteristics notes: 1. ac test inputs are driven at v cc q for a logic 1 and v ss for a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at v cc q/2. 3. output timing ends at v cc q/2. figure 34.1 ac input/output reference waveform note: all tests are performed with the outputs conf igured for full drive strength (bcr[5] = 0). figure 34.2 output load circuit table 34.1 output load circuit v cc qr1/r2 1.8v 2.7k ? output test points input (note 1) v cc q v ss v cc q /2 (note 2) v cc q/2 (note 3) dut v cc q r1 r2 30pf test point
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 171 advance information notes: 1. all tests are performed with the outputs conf igured for full drive strength (bcr[5] = 0). 2. see how extended timings impact cellularram? operation below. 3. high-z to low-z timings are tested with the circuit shown in figure 34.2 . the low-z timings measure a 4. 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 5. low-z to high-z timings are tested with the circuit shown in figure 34.2 . the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. table 34.2 asynchronous read cycle timing requirements parameter symbol 85ns/66 mhz 70ns/80 mhz units notes min max min max address access time t aa 85 70 ns adv# access time t aadv 85 70 ns page access time t apa 25 20 ns address hold from adv# high t avh 55ns address setup to adv# high t avs 10 10 ns lb#/ub# access time t ba 85 70 ns lb#/ub# disable to dq high-z output t bhz 88ns4 lb#/ub# enable to low-z output t blz 10 10 ns 3 ce# high between subsequent mixed-mode operations t cbph 55ns maximum ce# pulse width t cem 44s2 ce# low to wait valid t cew 17.517.5ns chip select access time t co 85 70 ns ce# low to adv# high t cvs 10 10 ns chip disable to dq and wait high-z output t hz 88ns4 chip enable to low-z output t lz 10 10 ns 3 output enable to valid output t oe 20 20 ns output hold from address change t oh 55ns output disable to dq high-z output t ohz 88ns4 output enable to low-z output t olz 55ns3 page cycle time t pc 25 20 ns read cycle time t rc 85 70 ns adv# pulse width low t vp 10 10 ns adv# pulse width high t vph 10 10 ns
172 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. all tests are performed with the outputs conf igured for full drive strength (bcr[5] = 0). 2. low-z to high-z timings are tested with the circuit shown in figure 34.2 . the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 3. high-z to low-z timings are tested with the circuit shown in figure 34.2 . the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . table 34.3 burst read cycle timing requirements parameter symbol 70ns/80 mhz 85ns/66 mhz units notes min max min max burst to read access time (variable latency) t aba 35 55 ns clk to output delay t aclk 911ns address setup to adv# high t avs 10 10 ns burst oe# low to output delay t boe 20 20 ns ce# high between subsequent mixed-mode operations t cbph 55ns ce# low to wait valid t cew 1 7.5 1 7.5 ns clk period t clk 12.5 15 ns ce# setup time to active clk edge t csp 45ns hold time from active clk edge t hd 22ns chip disable to dq and wait high-z output t hz 88ns2 clk rise or fall time t khkl 1.6 1.6 ns clk to wait valid t khtl 911ns clk to dq high-z output t khz 3838ns clk to low-z output t klz 2525ns output hold from clk t koh 22ns clk high or low time t kp 33ns output disable to dq high-z output t ohz 88ns2 output enable to low-z output t olz 55ns3 setup time to active clk edge t sp 33ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 173 advance information notes: 1. see how extended timings impact cellularram? operation below. 2. low-z to high-z timings are tested with the circuit shown in figure 34.2 . the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 3. high-z to low-z timings are tested with the circuit shown in figure 34.2 . the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . table 34.4 asynchronous write cycle timing requirements parameter symbol 70 ns/80 mhz 85 ns/66 mhz units notes min max min max address and adv# low setup time t as 00ns address hold from adv# going high t avh 55ns address setup to adv# going high t avs 10 10 ns address valid to end of write t aw 70 85 ns lb#/ub# select to end of write t bw 70 85 ns maximum ce# pulse width t cem 44s1 ce# low to wait valid t cew 1 7.5 1 7.5 ns async address-to-burst transition time t cka 70 85 ns ce# low to adv# high t cvs 10 10 ns chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data write setup time t dw 23 23 ns 1 chip disable to wait high-z output t hz 88ns chip enable to low-z output t lz 10 10 ns 3 end write to low-z output t ow 55ns3 adv# pulse width t vp 10 10 ns adv# pulse width high t vph 10 10 ns adv# setup to end of write t vs 70 85 ns write cycle time t wc 70 85 ns write to dq high-z output t whz 88ns2 write pulse width t wp 46 55 ns 1 write pulse width high t wph 10 10 ns write recovery time t wr 00ns
174 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 34.1 timing diagrams table 34.5 burst write cycle timing requirements parameter symbol 70ns/80 mhz 85ns/66 mhz units notes min max min max ce# high between subsequent mixed-mode operations t cbph 55ns ce# low to wait valid t cew 1 7.5 1 7.5 ns clock period t clk 12.5 15 ns ce# setup to clk active edge t csp 45ns hold time from active clk edge t hd 22ns chip disable to wait high-z output t hz 88ns clk rise or fall time t khkl 1.6 1.6 ns clock to wait valid t khtl 911ns clk high or low time t kp 33ns setup time to activate clk edge t sp 33ns figure 34.3 initialization period table 34.1 initialization timing parameters parameter symbol 70ns/80 mhz 85ns/66 mhz units notes min max min max initialization period (required before normal operations) t pu 150 150 s t pu v cc , v cc q = 1.7v v cc (min) device ready fo r normal operation
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 175 advance information figure 34.4 asynchronous read t olz t oe t lz t blz t ba t co t hz t aa high-z high-z t bhz t rc t ohz don't care undefined legend: valid address t cbph valid output t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] wait
176 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.2 asynchronous read timing parameters symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aa 70 85 ns t ba 70 85 ns t bhz 88ns t blz 10 10 ns t cbph 55ns t cew 17.517.5ns t co 70 ns t hz 88ns t lz 10 10 ns t oe 20 20 ns t ohz 88ns t olz 55ns t rc 70 85 ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 177 advance information figure 34.5 asynchronous read using adv# t olz t oe t lz t blz t ba t co t hz t aa high-z high-z t bhz t ohz don't care undefined legend: valid address t cbph valid output t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] wait t vph t avs t avh t cvs t vp t aadv
178 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.3 asynchronous read timing parameters using adv# symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aa 70 85 ns t aadv 70 85 ns t cvs 10 10 ns t avh 55ns t avs 10 10 ns t ba 70 85 ns t bhz 88ns t blz 10 10 ns t cbph 55ns t cew 17.517.5ns t co 70 85 ns t cvs 10 10 ns t hz 88ns t lz 10 10 ns t oe 20 20 ns t ohz 88ns t olz 55ns t vp 10 10 ns t vph 10 10 ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 179 advance information figure 34.6 page mode read t olz t oe t lz t blz t ba t hz t aa high-z high-z t bhz t ohz don't care undefined legend: t cbph t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] wait t pc t cem t co t rc t cbph valid address v ih v il a[3:0] valid address valid address valid address valid address t apa t oh valid output valid output valid output valid output
180 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.4 asynchronous read timing parameters?page mode operation symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aa 70 85 ns t apa 20 25 ns t ba 70 85 ns t bhz 88ns t blz 10 10 ns t cbph 55ns t cem 44s t cew 17.517.5ns t co 70 85 ns t hz 88ns t lz 10 10 ns t oe 20 20 ns t oh 55ns t ohz 88ns t olz 55ns t pc 20 25 ns t rc 70 85 ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 181 advance information note: non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. figure 34.7 single-access burst read operation?variable latency t ohz t olz t aclk t koh t hz high-z high-z don't care undefined legend: valid address valid output t khtl t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# v oh v ol v oh v ol dq[15:0] wait t sp t clk t csp t boe t aba t khkl t kp t kp v ih v il clk t sp t hd t hd t hd v ih v il oe# we# t sp t hd t sp t hd read burst identified (we# = high)
182 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.5 burst read timing parameters?single access, variable latency symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aba 35 55 ns t aclk 911ns t boe 20 20 ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t koh 22ns t kp 33ns t ohz 88ns t olz 55ns t sp 33ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 183 advance information note: non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. figure 34.8 four-word burst read operation?variable latency t ohz t olz high-z high-z t cbph don't care undefined legend: t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t sp t csp t boe t aba t sp t hd t hd v ih v il oe# we# t sp t hd t sp t hd read burst identified (we# = high) valid address t clk t khkl t kp t kp v ih v il clk t hd t hz valid output valid output valid output valid output t khtl t koh t aclk
184 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.6 burst read timing parameters?4-word burst symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aba 35 55 ns t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t koh 22ns t kp 33ns t ohz 88ns t olz 55ns t sp 33ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 185 advance information note: non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. figure 34.9 four-word burst read operation (with lb#/ub#) t ohz t olz high-z high-z t cbph don't care undefined legend: t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t sp t csp t boe t sp t hd t hd v ih v il oe# we# t sp t hd t sp t hd read burst identified (we# = high) valid address t clk v ih v il clk t hd t hz valid output valid output valid output t khtl t koh t aclk high-z t khtl t khtl t khtl
186 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information ta b l e 3 4 . 7 b u r s t r e a d t i m i n g p a r a meters?4-word burst with lb#/ub# symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khtl 911ns t khz 3838ns t klz 2525ns t koh 22ns t ohz 88ns t olz 55ns t sp 33ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 187 advance information figure 34.10 refresh collision during write operation notes: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. 2. oe# can stay low during burst suspend. if oe# is low, dq[15:0] will contin ue to output valid data. table 34.8 burst read timing parameters?burst suspend symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aclk 911ns t boe 20 20 ns t cbph 55ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t koh 22ns t ohz 88ns t olz 55ns t ohz t olz high-z high-z t cbph don't care undefined legend: t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# ce# lb#/ub# dq[15:0] wait t sp t csp t boe t sp t hd t hd v ih v il oe# we# t sp t hd t sp t hd t clk v ih v il clk t hz valid output valid output valid output valid output t koh t aclk (note 2) t boe t olz valid output valid output valid address t ohz valid address
188 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information t sp 33ns notes: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. 2. wait will assert lc + 1 or 2lc + 1 cycles for variable latency (depending upon refresh status). figure 34.9. continuous burst read showing an output delay with bcr[8] = 0 for end-of-row condition table 34.10 burst read timing parameters?bcr[8] = 0 symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aclk 911ns t clk 12.5 15 ns t khtl 911ns t koh 22ns table 34.8 burst read timing parameters?burst suspend (continued) symbol 70ns/80 mhz 85ns/66 mhz units min max min max t ohz don't care legend: v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# wait v ih v il oe# we# t clk v ih v il clk (note 2) t khtl t khtl v oh v ol dq[15:0] t koh t aclk valid output valid output valid output valid output
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 189 advance information figure 34.11 ce#-controlled asynchronous write t dh t wp t dw t whz t bw t aa high-z high-z t lz don't care legend: valid address t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] in wait t as t aw t wr t cw t cem t wph v oh v ol dq[15:0] out valid input
190 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.11 asynchronous write timing parameters?ce#-controlled symbol 70ns/80 mhz 85ns/66 mhz units min max min max t as 00ns t aw 70 85 ns t bw 70 85 ns t cem 44s t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t lz 10 10 ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 191 advance information figure 34.12 lb#/ub#-controlled asynchronous write t dh t wp t dw t whz t bw t wc high-z high-z t lz don't care legend: valid address t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] in wait t as t aw t wr t cw t cem t wph v oh v ol dq[15:0] out valid input
192 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.12 asynchronous write timi ng parameters?lb#/ub#-controlled symbol 70ns/80 mhz 85ns/66 mhz units min max min max t as 00ns t aw 70 85 ns t bw 70 85 ns t cem 44s t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t lz 10 10 ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 193 advance information figure 34.13 we#-controlled asynchronous write t dh t wp t dw t whz t bw t wc high-z high-z t lz don't care legend: valid address t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] in wait t aw t wr t cw t cem t wph v oh v ol dq[15:0] out valid input t ow t as
194 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.13 asynchronous write timing parameters?we#-controlled symbol 70ns/80 mhz 85ns/66 mhz units min max min max t as 00ns t aw 70 85 ns t bw 70 85 ns t cem 44s t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t lz 10 10 ns t ow 55ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 195 advance information figure 34.14 asynchronous write using adv# t dh t wp t dw t whz t bw high-z high-z t lz don't care legend: t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] in wait t avs t cw t cem t wph v oh v ol dq[15:0] out valid input t ow t as valid address t aw t avh t vs t vp t vph t as
196 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.14 asynchronous write timing parameters using adv# symbol 70ns/80 mhz 85ns/66 mhz units min max min max t as 00ns t avh 55ns t avs 10 10 ns t aw 70 85 ns t bw 70 85 ns t cem 44s t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t lz 10 10 ns t ow 55ns t as 00ns t vp 10 10 ns t vph 10 10 ns t vs 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 197 advance information notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay; burst length four; bu rst wrap enabled. figure 34.15 burst write operation t ohz high-z don't care legend: t cew high-z v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# dq[15:0] wait t sp t sp t hd t hd v ih v il oe# we# t sp t hd v ih v il lb#/ub# t sp t hd read burst identified (we# = low) t clk t khkl t kp t kp v ih v il clk t hz t khtl t hd t sp valid address t cbph v ih v il ce# t csp t hd (note 2) d[1] d[2] d[3] d[0]
198 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.15 burst write timing parameters symbol 70ns/80 mhz 85ns/66 mhz units min max min max t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t kp 33ns t sp 33ns notes: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. 2. wait will assert lc + 1 or 2lc + 1 cycles for variable latency (depending upon refresh status). figure 34.16 continuous burst write showing an output delay with bcr[8] = 0 for end-of-row condition don't care legend: v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# wait t clk v ih v il clk (note 2) v ih v il oe# t ohz v ih v il we# t khtl t khtl v oh v ol dq[15:0] t hd t sp valid input d[n] valid input d[n+1] valid input d[n+3] valid input d[n+2] end of row
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 199 advance information table 34.16 burst write timing parameters?bcr[8] = 0 symbol 70ns/80 mhz 85ns/66 mhz units min max min max t clk 12.5 15 ns t hd 22ns t khtl 811ns t sp 33ns notes: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. 1. to allow self-refresh operations to occur between transactions, ce# must remain high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. ce# can stay low between burst read and burst write operations. see how extended timings impact cellularram? operation for restrictions on the maximum ce# low time (t cem ). figure 34.17 burst write followed by burst read table 34.17 write timing parameters?burst write followed by burst read symbol 70ns/80 mhz 85ns/66 mhz units min max min max t cbph 55ns t clk 12.5 20 15 20 ns t csp 4 20520ns t hd 22ns t sp 33ns t ohz high-z high-z t cbph high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# l b#/ub# d q[15:0] wait t sp t csp t sp t hd t hd v ih v il oe# we# t sp t hd t clk v ih v il clk t hd t boe valid address t sp t hd valid address t sp t hd (note 2) t csp t sp t hd t sp t hd d[0] d[3] d[2] d[1] valid output valid output valid output valid output v oh v ol t koh t aclk t sp t hd high-z don't care undefine d legend:
200 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information table 34.18 read timing parameters?burst write followed by burst read symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aclk 911ns t boe 20 20 ns t clk 12.5 15 ns t csp 45ns t hd 22ns t koh 22ns t ohz 88ns t sp 33ns notes: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. 1. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. if ce# goes high, it must re main high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see how extended timings impact cellularram? operation for restrictions on the maximum ce# low time (t cem ). figure 34.18 asynchronous write followed by burst read t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t csp t sp t hd v ih v il oe# we# t sp t hd t clk v ih v il clk t boe valid address t wc t wc (note 2) t wp t wph t sp t hd valid output valid output valid output valid output v oh v ol t koh t aclk high-z don't care undefined legend: valid address valid address t cka t sp t hd t bw t cw t aw t wr t cbph t wc t cew data t whz data t vph t avs t avh t vp t vs t cvs t as t dh t dw
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 201 advance information table 34.19 write timing parameters?asynchronous write followed by burst read symbol 70ns/80 mhz 85ns/66 mhz units min max min max t avh 55ns t as 00ns t avs 10 10 ns t aw 70 85 ns t bw 70 85 ns t cka 70 85 ns t cvs 10 10 ns t cw 70 85 ns t dh 00ns t dw 20 23 ns t vp 10 10 ns t vph 10 10 ns t vs 70 85 ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns table 34.20 read timing parameters?asynchronous write followed by burst read symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t koh 22ns t ohz 88ns t sp 33ns
202 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. if ce# goes high, it must re main high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see how extended timings impact cellularram? operation for restrictions on the maximum ce# low time (t cem ). figure 34.19 asynchronous write (adv# low) followed by burst read t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t csp t sp t hd v ih v il oe# we# t sp t hd t clk v ih v il clk t boe valid address t wc t wc (note 2) t wp t wph t sp t hd valid output valid output valid output valid output v oh v ol t koh t aclk high-z don't care undefined legend: valid address valid address t cka t sp t hd t bw t cw t aw t wr t csp t wc t cew data t dh t whz data t dw
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 203 advance information table 34.21 asynchronous write timing parameters?adv# low symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aw 70 85 ns t bw 70 85 ns t cka 70 85 ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns table 34.22 burst read timing parameters symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t koh 22ns t ohz 88ns t sp 33ns
204 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. if ce# goes high, it must re main high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see how extended timings impact cellularram? operation for restrictions on the maximum ce# low time (t cem ). figure 34.23. burst read followed by asynchronous write (we#-controlled) valid address t sp t hd t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# dq[15:0] wait t hd t wc v ih v il oe# we# t clk v ih v il clk t sp t hd (note 2) t wp t wph t sp t hd valid output t cbph t koh t aclk don't care undefined legend: valid address v ih v il lb#/ub# t olz t aw t wr t csp t bw t dh t khtl t dw t sp t hd t hz t boe t cem t cw t as t cew t cew t hz read burst identified (we# = high) high-z valid input
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 205 advance information table 34.24 burst read timing parameters symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t koh 22ns t kp 33ns t ohz 88ns table 34.25 asynchronous write timing parameters?we# controlled symbol 70ns/80 mhz 85ns/66 mhz units min max min max t as 00ns t aw 70 85 ns t bw 70 85 ns t cem 44s t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t wc 70 85 ns t wp 46 55 ns t wph 10 10 ns t wr 00ns
206 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information notes: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. if ce# goes high, it must re main high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see how extended timings impact cellularram? operation for restrictions on the maximum ce# low time (t cem ). figure 34.26. burst read followed by asynchronous write using adv# valid address t sp t hd t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol a[22:0] adv# ce# dq[15:0] wait t hd v ih v il oe# we# t clk v ih v il clk t sp t hd (note 2) t wp t wph t sp t hd valid output valid input t cbph t koh t aclk don't care undefined legend: valid address t as v ih v il lb#/ub# t olz t avs t avh t csp t bw t dh t khtl t dw t sp t hd t hz t boe t cem t aw t cw t vs t vp t vph t as t cew t cew t hz read burst identified (we# = high) high-z
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 207 advance information table 34.27 burst read timing parameters symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t koh 22ns t kp 33ns t ohz 88ns table 34.28 asynchronous write timing parameters using adv# symbol 70ns/80 mhz 85ns/66 mhz units min max min max t as 00ns t avh 55ns t avs 10 10 ns t aw 70 85 ns t bw 70 85 ns t cem 44s t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t vp 10 10 ns t vph 10 10 ns t vs 70 85 ns t wp 46 55 ns t wph 10 10 ns t wr 00ns
208 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information note: ce# can stay low when transitioning between asynchronous operations. if ce# goes high, it must remain high for at least 5ns (t cbph ) to schedule the appropriate in ternal refresh operation. see how extended timings impact cel- lularram? operation for restrictions on the maximum ce# low time (t cem ). figure 34.29. asynchronous write followed by asynchronous read?adv# low t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t cem v ih v il oe# we# t blz t oe valid address (note) t wp t wph valid output v oh v ol t olz don't care undefined legend: valid address valid address t bw t cw t aw t wr t cbph t wc data t whz data t as t dh t dw t hz t hz t bhz t aa t hz t lz
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 209 advance information table 34.30 write timing parameters?adv# low symbol 70ns/80 mhz 85ns/66 mhz units min max min max t as 00ns t aw 70 85 ns t bw 70 85 ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns table 34.31 read timing parameters?adv# low symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aa 70 85 ns t bhz 88ns t blz 10 10 ns t cbph 55ns t cem 44s t hz 88ns t lz 10 10 ns t oe 20 20 ns t ohz 88ns t olz 55ns
210 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information note: ce# can stay low when transitioning between asynchronous operations. if ce# goes high, it must remain high for at least 5ns (t cbph ) to schedule the appropriate in ternal refresh operation. see how extended timings impact cel- lularram? operation for restrictions on the maximum ce# low time (t cem ). figure 34.32. asynchronous write followed by asynchronous read t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t cem v ih v il oe# we# t blz t olz valid address (note) t wp t wph valid output v oh v ol t oe don't care undefined legend: valid address valid address t bw t cw t aw t wr t cbph t wc data t whz data t as t dh t dw t bhz t aa t hz t lz t avs t avh t vph t vp t vs t cvs t as
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 211 advance information table 34.33 write timing parameters?asynchronous write followed by asynchronous read symbol 70ns/80 mhz 85ns/66 mhz units min max min max t as 00ns t avh 55ns t avs 10 10 ns t aw 70 85 ns t bw 70 85 ns t cvs 10 10 ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t vp 10 10 ns t vph 10 10 ns t vs 70 85 ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns table 34.34 read timing parameters?asynchronous write followed by asynchronous read symbol 70ns/80 mhz 85ns/66 mhz units min max min max t aa 70 85 ns t bhz 88ns t blz 10 10 ns t cbph 55ns t cem 44s t hz 88ns t lz 10 10 ns t oe 20 20 ns t ohz 88ns t olz 55ns
212 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 35 how extended timings impact cellularram? operation 35.1 introduction this section describes cellularram? timing requirements in systems that perform extended operations. cellularram products use a dram technology that periodically requires refresh to ensure against data corruption. cellularram devices include on-chi p circuitry that performs the required refresh in a manner that is completely transparent in systems with normal bus timings. the refresh cir- cuitry imposes constraints on timings in systems that take longer than 4s to complete an operation. write operations are affected if the device is configured for asynchronous operation. both read and write operations are affected if the device is configured for page or burst-mode operation. 35.2 asynchronous write operation the timing parameters provided in figure 34.4 require that all write operations must be com- pleted within 4s. after completing a write oper ation, the device must either enter standby (by transitioning ce# high), or else perform a second operation (read or write) using a new address. figure 35.1 and figure 35.2 demonstrate these constraints as they apply during an asynchronous (page-mode-disabled) operation. either the ce# active period (t cem in figure 35.1 ) or the ad- dress valid period (t tm in figure 35.2 ) must be less than 4s during any write operation, otherwise, the extended write timings must be used. figure 35.1 extended timing for t cem figure 35.2 extended timing for t tm table 35.1 extended cycle impact on read and write cycles page mode timing constraint read cycle write cycle asynchronous page mode disabled t cem and t tm > 4s (see figure 35.1 and figure 35.2 .) no impact. must use extended write timing. (see figure 35.2 ) asynchronous page mode enabled t cem > 4s (see figure 35.1 .) all following intrapage read access times are t aa (not t apa ). must use extended write timing. (see figure 35.3 ) burst t cem > 4s (see figure 35.1 .) burst must cross a row boundary within 4s. ce# address t cem 4 s < ce# address tm < t 4 s
february 17, 2005 s75ws-n-00_a0 s75ws256nxx based mcps 213 advance information 35.2.1 extended write timing? asynchronous write operation modified timings are required during extended write operations (see figure 35.3 ). an extended write operation requires that both the write pulse width (t wp ) and the data valid period (t dw ) be lengthened to at least the minimum write cycle time (t wc [min]). these increased timings ensure that time is available for both a refresh operation and a successful completion of the write operation. 35.3 page mode read operation when a cellularram device is configured for page mode operation, the address inputs are used to accelerate read accesses and cannot be used by the on-chip circuitry to schedule refresh. if ce# is low longer than the t cem maximum time of 4s during a read operation, the system must allow t aa (not t apa , as would otherwise be expected) for all subsequent intrapage accesses until ce# goes high. 35.4 burst-mode operation when configured for burst-mode operation, it is necessary to allow the device to perform a refresh within any 4s window. one of two conditions will enable the device to schedule a refresh within 4s. the first condition is when all burst operatio ns complete within 4s. a burst completes when the ce# signal is registered high on a rising clock edge. the second condition that allows a refresh is when a burst access crosses a row boundary. the row-boundary crossing causes wait to be asserted while the next row is accessed and enables the scheduling of refresh. 35.5 summary cellularram products are designed to ensure that any possible asynchronous timings do not cause data corruption due to lack of refresh. slow bus timings on asynchronous write operations require that t wp and t dw be lengthened. slow bus timings du ring asynchronous page read oper- ations cause the next intrapage read data to be delayed to t aa . burst mode timings must allow the device to perform a refresh within any 4s period. a burst operation must either complete (ce# registered high) or cross a row boundary within 4s to en- sure successful refresh scheduling. these timing requ irements are likely to have little or no impact when interfacing a cellularram device with a low-speed memory bus. figure 35.3 extended write operation t cem or t tm > 4 s t wp > t wc (min) t dw > t wc (min) address ce# lb#/ub# we# data-in
214 s75ws256nxx based mcps s75ws-n-00_a0 february 17, 2005 advance information 36 revisions revision a0 (february 17, 2005) initial release colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, deve loped and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuclear reaction control in nucle ar facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporatin g safety design measures into your facility and equipment such as re dundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty , express, implied, or stat utory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2004-2005 spansion llc. all righ ts reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion l lc. other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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